tree dc65ef2b993ededd9ecb0cc5759dea858547aee4
parent 0ab0885de0dceb4e23e01665e975f283e5732dc3
author Craig Topper <craig.topper@intel.com> 1547675192 +0000
committer Craig Topper <craig.topper@intel.com> 1547675192 +0000

[X86] Add X86ISD::VSHLV and X86ISD::VSRLV nodes for psllv and psrlv

Previously we used ISD::SHL and ISD::SRL to represent these in SelectionDAG. ISD::SHL/SRL interpret an out of range shift amount as undefined behavior and will constant fold to undef. While the intrinsics are defined to return 0 for out of range shift amounts. A previous patch added a special node for VPSRAV to produce all sign bits.

This was previously believed safe because undefs frequently get turned into 0 either from the constant pool or a desire to not have a false register dependency. But undef is treated specially in some optimizations. For example, its ignored in detection of vector splats. So if the ISD::SHL/SRL can be constant folded and all of the elements with in bounds shift amounts are the same, we might fold it to single element broadcast from the constant pool. This would not put 0s in the elements with out of bounds shift amounts.

We do have an existing InstCombine optimization to use shl/lshr when the shift amounts are all constant and in bounds. That should prevent some loss of constant folding from this change.

Patch by zhutianyang and Craig Topper

Differential Revision: https://reviews.llvm.org/D56695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351381 91177308-0d34-0410-b5e6-96231b3b80d8