commit 0ab0885de0dceb4e23e01665e975f283e5732dc3
author Craig Topper <craig.topper@intel.com> Wed Jan 16 21:46:28 2019 +0000
committer Craig Topper <craig.topper@intel.com> Wed Jan 16 21:46:28 2019 +0000
tree c9b6d5fe3879a465595c8b7f77ff4bfd209a6c19
parent 17717539b05ea0b66de7399d73c2f89103127ea0

[X86] Use X86ISD::BLENDV for blendv intrinsics. Replace vselect with blendv just before isel table lookup. Remove vselect isel patterns.

This cleans up the duplication we have with both intrinsic isel patterns and vselect isel patterns. This should also allow the intrinsics to get SimplifyDemandedBits support for the condition.

I've switched the canonical pattern in isel to use the X86ISD::BLENDV node instead of VSELECT. Since it always seemed weird to move from BLENDV with its relaxed rules on condition bits to VSELECT which has strict rules about all bits of the condition element being the same. Its more correct to go from VSELECT to BLENDV.

Differential Revision: https://reviews.llvm.org/D56771

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351380 91177308-0d34-0410-b5e6-96231b3b80d8