AMDGPU: Fix SMEM WAR hazard for gfx10 readlane
Summary: Hazard recognizer fails to see hazard with V_READLANE_B32_gfx10.
Reviewers: rampitec
Reviewed By: rampitec
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375265 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 958b801..9528aee 100644
--- a/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -952,6 +952,7 @@
unsigned SDSTName;
switch (MI->getOpcode()) {
case AMDGPU::V_READLANE_B32:
+ case AMDGPU::V_READLANE_B32_gfx10:
case AMDGPU::V_READFIRSTLANE_B32:
SDSTName = AMDGPU::OpName::vdst;
break;
diff --git a/test/CodeGen/AMDGPU/smem-war-hazard.mir b/test/CodeGen/AMDGPU/smem-war-hazard.mir
index 0796754..531cca1 100644
--- a/test/CodeGen/AMDGPU/smem-war-hazard.mir
+++ b/test/CodeGen/AMDGPU/smem-war-hazard.mir
@@ -304,6 +304,21 @@
S_ENDPGM 0
...
+# Workaround since spilling/restoring SGPRs use real opcodes.
+# GCN-LABEL: name: hazard_smem_war_readlane_gfx10
+# GCN: S_LOAD_DWORD_IMM
+# GCN: $sgpr_null = S_MOV_B32 0
+# GCN-NEXT: V_READLANE_B32_gfx10
+---
+name: hazard_smem_war_readlane_gfx10
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0
+ $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ $sgpr0 = V_READLANE_B32_gfx10 $vgpr0, $sgpr3
+ S_ENDPGM 0
+...
+
# GCN-LABEL: name: hazard_smem_war_readfirstlane
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0