test/CodeGen/X86/GlobalISel/select-merge-vec512.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
  define void @test_merge_v128() {
    ret void
  }

  define void @test_merge_v256() {
    ret void
  }

...
---
name:            test_merge_v128
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
body:             |
  bb.1 (%ir-block.0):

    ; ALL-LABEL: name: test_merge_v128
    ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
    ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]]
    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1
    ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
    ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
    ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr2]]
    ; ALL: RET 0, implicit $zmm0
    %0(<4 x s32>) = IMPLICIT_DEF
    %1(<16 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>)
    $zmm0 = COPY %1(<16 x s32>)
    RET 0, implicit $zmm0

...
---
name:            test_merge_v256
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
body:             |
  bb.1 (%ir-block.0):

    ; ALL-LABEL: name: test_merge_v256
    ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
    ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]]
    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1
    ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]]
    ; ALL: RET 0, implicit $zmm0
    %0(<8 x s32>) = IMPLICIT_DEF
    %1(<16 x s32>) = G_CONCAT_VECTORS %0(<8 x s32>), %0(<8 x s32>)
    $zmm0 = COPY %1(<16 x s32>)
    RET 0, implicit $zmm0

...