tree 06cda5cd76446e48caa8c552c11717f10f5f2cb7
parent baeeed43cc24472e1cbc83fb0b6ee0f70eef8e1f
author Roland Froese <froese@ca.ibm.com> 1549906154 +0000
committer Roland Froese <froese@ca.ibm.com> 1549906154 +0000

[PowerPC] Avoid scalarization of vector truncate

The PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead.

Differential Revision: https://reviews.llvm.org/D56507


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353724 91177308-0d34-0410-b5e6-96231b3b80d8