# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |

  define i1 @fcmp_float_oeq(float %x, float %y) {
    %1 = fcmp oeq float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_ogt(float %x, float %y) {
    %1 = fcmp ogt float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_oge(float %x, float %y) {
    %1 = fcmp oge float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_olt(float %x, float %y) {
    %1 = fcmp olt float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_ole(float %x, float %y) {
    %1 = fcmp ole float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_one(float %x, float %y) {
    %1 = fcmp one float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_ord(float %x, float %y) {
    %1 = fcmp ord float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_uno(float %x, float %y) {
    %1 = fcmp uno float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_ueq(float %x, float %y) {
    %1 = fcmp ueq float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_ugt(float %x, float %y) {
    %1 = fcmp ugt float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_uge(float %x, float %y) {
    %1 = fcmp uge float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_ult(float %x, float %y) {
    %1 = fcmp ult float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_ule(float %x, float %y) {
    %1 = fcmp ule float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_float_une(float %x, float %y) {
    %1 = fcmp une float %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_oeq(double %x, double %y) {
    %1 = fcmp oeq double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_ogt(double %x, double %y) {
    %1 = fcmp ogt double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_oge(double %x, double %y) {
    %1 = fcmp oge double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_olt(double %x, double %y) {
    %1 = fcmp olt double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_ole(double %x, double %y) {
    %1 = fcmp ole double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_one(double %x, double %y) {
    %1 = fcmp one double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_ord(double %x, double %y) {
    %1 = fcmp ord double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_uno(double %x, double %y) {
    %1 = fcmp uno double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_ueq(double %x, double %y) {
    %1 = fcmp ueq double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_ugt(double %x, double %y) {
    %1 = fcmp ugt double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_uge(double %x, double %y) {
    %1 = fcmp uge double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_ult(double %x, double %y) {
    %1 = fcmp ult double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_ule(double %x, double %y) {
    %1 = fcmp ule double %x, %y
    ret i1 %1
  }

  define i1 @fcmp_double_une(double %x, double %y) {
    %1 = fcmp une double %x, %y
    ret i1 %1
  }

...
---
name:            fcmp_float_oeq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_oeq
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
    ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
    ; CHECK: $al = COPY [[AND8rr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(oeq), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_ogt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_ogt
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ogt), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_oge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_oge
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(oge), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_olt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_olt
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(olt), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_ole
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_ole
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ole), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_one
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_one
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(one), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_ord
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_ord
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ord), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_uno
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_uno
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(uno), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_ueq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_ueq
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ueq), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_ugt
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ugt), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_uge
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(uge), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_ult
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ult), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_ule
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ule), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_float_une
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_float_une
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
    ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
    ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
    ; CHECK: $al = COPY [[OR8rr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s32) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s32) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(une), %0(s32), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_oeq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_oeq
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
    ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
    ; CHECK: $al = COPY [[AND8rr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(oeq), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_ogt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_ogt
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ogt), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_oge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_oge
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(oge), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_olt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_olt
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(olt), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_ole
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_ole
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ole), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_one
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_one
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(one), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_ord
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_ord
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ord), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_uno
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_uno
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(uno), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_ueq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_ueq
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ueq), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_ugt
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ugt), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_uge
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(uge), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_ult
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ult), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_ule
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
    ; CHECK: $al = COPY [[SETCCr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(ule), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...
---
name:            fcmp_double_une
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
  - { id: 3, class: vecr }
  - { id: 4, class: _ }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: fcmp_double_une
    ; CHECK: liveins: $xmm0, $xmm1
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
    ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
    ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
    ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
    ; CHECK: $al = COPY [[OR8rr]]
    ; CHECK: RET 0, implicit $al
    %2:vecr(s128) = COPY $xmm0
    %0:vecr(s64) = G_TRUNC %2(s128)
    %3:vecr(s128) = COPY $xmm1
    %1:vecr(s64) = G_TRUNC %3(s128)
    %6:gpr(s8) = G_FCMP floatpred(une), %0(s64), %1
    %5:gpr(s8) = COPY %6(s8)
    $al = COPY %5(s8)
    RET 0, implicit $al

...