test/CodeGen/X86/GlobalISel/select-undef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |

  define i8 @test() {
    ret i8 undef
  }

  define i8 @test2(i8 %a) {
    %r = add i8 %a, undef
    ret i8 %r
  }

  define float @test3() {
    ret float undef
  }
...
---
name:            test
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1 (%ir-block.0):
    ; ALL-LABEL: name: test
    ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
    ; ALL: $al = COPY [[DEF]]
    ; ALL: RET 0, implicit $al
    %0(s8) = G_IMPLICIT_DEF
    $al = COPY %0(s8)
    RET 0, implicit $al

...
---
name:            test2
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; ALL-LABEL: name: test2
    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
    ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
    ; ALL: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[DEF]], implicit-def $eflags
    ; ALL: $al = COPY [[ADD8rr]]
    ; ALL: RET 0, implicit $al
    %0(s8) = COPY $dil
    %1(s8) = G_IMPLICIT_DEF
    %2(s8) = G_ADD %0, %1
    $al = COPY %2(s8)
    RET 0, implicit $al

...
---
name:            test3
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 1, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    ; ALL-LABEL: name: test3
    ; ALL: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
    ; ALL: $xmm0 = COPY [[DEF]]
    ; ALL: RET 0, implicit $xmm0
    %1:vecr(s128) = G_IMPLICIT_DEF
    $xmm0 = COPY %1:vecr(s128)
    RET 0, implicit $xmm0

...