test/CodeGen/X86/GlobalISel/select-add-x32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=X32
--- |
  define i64 @test_add_i64(i64 %a, i64 %b) {
    %r = add i64 %a, %b
    ret i64 %r
  }

...
---
name:            test_add_i64
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
  - { id: 5, class: gpr }
  - { id: 6, class: gpr }
  - { id: 7, class: gpr }
  - { id: 8, class: gpr }
  - { id: 9, class: gpr }
body:             |
  bb.0 (%ir-block.0):
    ; X32-LABEL: name: test_add_i64
    ; X32: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; X32: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; X32: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; X32: [[DEF3:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; X32: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[DEF]], [[DEF2]], implicit-def $eflags
    ; X32: [[COPY:%[0-9]+]]:gr32 = COPY $eflags
    ; X32: $eflags = COPY [[COPY]]
    ; X32: [[ADC32rr:%[0-9]+]]:gr32 = ADC32rr [[DEF1]], [[DEF3]], implicit-def $eflags, implicit $eflags
    ; X32: [[COPY1:%[0-9]+]]:gr32 = COPY $eflags
    ; X32: $eax = COPY [[ADD32rr]]
    ; X32: $edx = COPY [[ADC32rr]]
    ; X32: RET 0, implicit $eax, implicit $edx
    %0(s32) = IMPLICIT_DEF
    %1(s32) = IMPLICIT_DEF
    %2(s32) = IMPLICIT_DEF
    %3(s32) = IMPLICIT_DEF
    %9(s8) = G_CONSTANT i8 0
    %4(s1) = G_TRUNC %9(s8)
    %5(s32), %6(s1) = G_UADDE %0, %2, %4
    %7(s32), %8(s1) = G_UADDE %1, %3, %6
    $eax = COPY %5(s32)
    $edx = COPY %7(s32)
    RET 0, implicit $eax, implicit $edx

...