# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOT_AVX2 --check-prefix=SSE2
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx  -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOT_AVX2 --check-prefix=AVX1
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2

--- |
  define void @test_add_v32i8() {
    %ret = add <32 x i8> undef, undef
    ret void
  }

  define void @test_add_v16i16() {
    %ret = add <16 x i16> undef, undef
    ret void
  }

  define void @test_add_v8i32() {
    %ret = add <8 x i32> undef, undef
    ret void
  }

  define void @test_add_v4i64() {
    %ret = add <4 x i64> undef, undef
    ret void
  }

...
---
name:            test_add_v32i8
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1
    ; SSE2-LABEL: name: test_add_v32i8
    ; SSE2: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
    ; SSE2: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
    ; SSE2: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
    ; SSE2: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
    ; SSE2: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV2]]
    ; SSE2: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV3]]
    ; SSE2: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)
    ; SSE2: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
    ; SSE2: RET 0
    ; AVX1-LABEL: name: test_add_v32i8
    ; AVX1: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
    ; AVX1: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
    ; AVX1: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
    ; AVX1: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
    ; AVX1: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV2]]
    ; AVX1: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV3]]
    ; AVX1: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)
    ; AVX1: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
    ; AVX1: RET 0
    ; AVX2-LABEL: name: test_add_v32i8
    ; AVX2: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
    ; AVX2: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
    ; AVX2: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[DEF]], [[DEF1]]
    ; AVX2: $ymm0 = COPY [[ADD]](<32 x s8>)
    ; AVX2: RET 0
    %0(<32 x s8>) = IMPLICIT_DEF
    %1(<32 x s8>) = IMPLICIT_DEF
    %2(<32 x s8>) = G_ADD %0, %1
    $ymm0 = COPY %2
    RET 0

...
---
name:            test_add_v16i16
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1
    ; SSE2-LABEL: name: test_add_v16i16
    ; SSE2: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
    ; SSE2: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
    ; SSE2: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
    ; SSE2: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
    ; SSE2: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV2]]
    ; SSE2: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV1]], [[UV3]]
    ; SSE2: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>)
    ; SSE2: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
    ; SSE2: RET 0
    ; AVX1-LABEL: name: test_add_v16i16
    ; AVX1: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
    ; AVX1: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
    ; AVX1: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
    ; AVX1: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
    ; AVX1: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV2]]
    ; AVX1: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV1]], [[UV3]]
    ; AVX1: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>)
    ; AVX1: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
    ; AVX1: RET 0
    ; AVX2-LABEL: name: test_add_v16i16
    ; AVX2: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
    ; AVX2: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
    ; AVX2: [[ADD:%[0-9]+]]:_(<16 x s16>) = G_ADD [[DEF]], [[DEF1]]
    ; AVX2: $ymm0 = COPY [[ADD]](<16 x s16>)
    ; AVX2: RET 0
    %0(<16 x s16>) = IMPLICIT_DEF
    %1(<16 x s16>) = IMPLICIT_DEF
    %2(<16 x s16>) = G_ADD %0, %1
    $ymm0 = COPY %2
    RET 0

...
---
name:            test_add_v8i32
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1
    ; SSE2-LABEL: name: test_add_v8i32
    ; SSE2: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; SSE2: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; SSE2: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
    ; SSE2: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
    ; SSE2: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV2]]
    ; SSE2: [[ADD1:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV1]], [[UV3]]
    ; SSE2: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>)
    ; SSE2: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
    ; SSE2: RET 0
    ; AVX1-LABEL: name: test_add_v8i32
    ; AVX1: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; AVX1: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; AVX1: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
    ; AVX1: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
    ; AVX1: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV2]]
    ; AVX1: [[ADD1:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV1]], [[UV3]]
    ; AVX1: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>)
    ; AVX1: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
    ; AVX1: RET 0
    ; AVX2-LABEL: name: test_add_v8i32
    ; AVX2: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; AVX2: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; AVX2: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[DEF]], [[DEF1]]
    ; AVX2: $ymm0 = COPY [[ADD]](<8 x s32>)
    ; AVX2: RET 0
    %0(<8 x s32>) = IMPLICIT_DEF
    %1(<8 x s32>) = IMPLICIT_DEF
    %2(<8 x s32>) = G_ADD %0, %1
    $ymm0 = COPY %2
    RET 0

...
---
name:            test_add_v4i64
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1
    ; SSE2-LABEL: name: test_add_v4i64
    ; SSE2: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; SSE2: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; SSE2: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
    ; SSE2: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
    ; SSE2: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV]], [[UV2]]
    ; SSE2: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV1]], [[UV3]]
    ; SSE2: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>)
    ; SSE2: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
    ; SSE2: RET 0
    ; AVX1-LABEL: name: test_add_v4i64
    ; AVX1: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; AVX1: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; AVX1: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
    ; AVX1: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
    ; AVX1: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV]], [[UV2]]
    ; AVX1: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV1]], [[UV3]]
    ; AVX1: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>)
    ; AVX1: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
    ; AVX1: RET 0
    ; AVX2-LABEL: name: test_add_v4i64
    ; AVX2: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; AVX2: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; AVX2: [[ADD:%[0-9]+]]:_(<4 x s64>) = G_ADD [[DEF]], [[DEF1]]
    ; AVX2: $ymm0 = COPY [[ADD]](<4 x s64>)
    ; AVX2: RET 0
    %0(<4 x s64>) = IMPLICIT_DEF
    %1(<4 x s64>) = IMPLICIT_DEF
    %2(<4 x s64>) = G_ADD %0, %1
    $ymm0 = COPY %2
    RET 0

...