test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

  define void @sdiv_i32() {entry: ret void}
  define void @srem_i32() {entry: ret void}
  define void @udiv_i32() {entry: ret void}
  define void @urem_i32() {entry: ret void}

...
---
name:            sdiv_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: sdiv_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[PseudoSDIV:%[0-9]+]]:acc64 = PseudoSDIV [[COPY1]], [[COPY]]
    ; MIPS32: [[PseudoMFLO:%[0-9]+]]:gpr32 = PseudoMFLO [[PseudoSDIV]]
    ; MIPS32: $v0 = COPY [[PseudoMFLO]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_SDIV %1, %0
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            srem_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: srem_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[PseudoSDIV:%[0-9]+]]:acc64 = PseudoSDIV [[COPY1]], [[COPY]]
    ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoSDIV]]
    ; MIPS32: $v0 = COPY [[PseudoMFHI]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_SREM %1, %0
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            udiv_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: udiv_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[PseudoUDIV:%[0-9]+]]:acc64 = PseudoUDIV [[COPY1]], [[COPY]]
    ; MIPS32: [[PseudoMFLO:%[0-9]+]]:gpr32 = PseudoMFLO [[PseudoUDIV]]
    ; MIPS32: $v0 = COPY [[PseudoMFLO]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_UDIV %1, %0
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            urem_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: urem_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[PseudoUDIV:%[0-9]+]]:acc64 = PseudoUDIV [[COPY1]], [[COPY]]
    ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoUDIV]]
    ; MIPS32: $v0 = COPY [[PseudoMFHI]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_UREM %1, %0
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...