# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

  define void @and_i32() {entry: ret void}
  define void @or_i32() {entry: ret void}
  define void @xor_i32() {entry: ret void}
  define void @shl(i32) {entry: ret void}
  define void @ashr(i32) {entry: ret void}
  define void @lshr(i32) {entry: ret void}
  define void @shlv(i32, i32) {entry: ret void}
  define void @ashrv(i32, i32) {entry: ret void}
  define void @lshrv(i32, i32) {entry: ret void}

...
---
name:            and_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: and_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY1]], [[COPY]]
    ; MIPS32: $v0 = COPY [[AND]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_AND %1, %0
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            or_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: or_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]]
    ; MIPS32: $v0 = COPY [[OR]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_OR %1, %0
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            xor_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: xor_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]]
    ; MIPS32: $v0 = COPY [[XOR]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_XOR %1, %0
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            shl
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: shl
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[COPY]], 1
    ; MIPS32: $v0 = COPY [[SLL]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = G_CONSTANT i32 1
    %2:gprb(s32) = G_SHL %0, %1
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            ashr
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: ashr
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY]], 1
    ; MIPS32: $v0 = COPY [[SRA]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = G_CONSTANT i32 1
    %2:gprb(s32) = G_ASHR %0, %1
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            lshr
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: lshr
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY]], 1
    ; MIPS32: $v0 = COPY [[SRL]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = G_CONSTANT i32 1
    %2:gprb(s32) = G_LSHR %0, %1
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            shlv
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: shlv
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[SLLV:%[0-9]+]]:gpr32 = SLLV [[COPY]], [[COPY1]]
    ; MIPS32: $v0 = COPY [[SLLV]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_SHL %0, %1
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            ashrv
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: ashrv
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[SRAV:%[0-9]+]]:gpr32 = SRAV [[COPY]], [[COPY1]]
    ; MIPS32: $v0 = COPY [[SRAV]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_ASHR %0, %1
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            lshrv
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: lshrv
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[SRLV:%[0-9]+]]:gpr32 = SRLV [[COPY]], [[COPY1]]
    ; MIPS32: $v0 = COPY [[SRLV]]
    ; MIPS32: RetRA implicit $v0
    %0:gprb(s32) = COPY $a0
    %1:gprb(s32) = COPY $a1
    %2:gprb(s32) = G_LSHR %0, %1
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...