test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s

---
name: test_intrinsic_round_s32
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_intrinsic_round_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_INTRINSIC_ROUND %0
    $vgpr0 = COPY %0
...

---
name: test_intrinsic_round_s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_intrinsic_round_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[INTRINSIC_ROUND]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_INTRINSIC_ROUND %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_intrinsic_round_v2s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_intrinsic_round_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[UV]]
    ; CHECK: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[UV1]]
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INTRINSIC_ROUND]](s32), [[INTRINSIC_ROUND1]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_intrinsic_round_v2s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3

    ; CHECK-LABEL: name: test_intrinsic_round_v2s64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
    ; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[UV]]
    ; CHECK: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[UV1]]
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INTRINSIC_ROUND]](s64), [[INTRINSIC_ROUND1]](s64)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...