# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s

---
name: extract_vector_elt_0_v2i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: extract_vector_elt_0_v2i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v3i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2
    ; CHECK-LABEL: name: extract_vector_elt_0_v3i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<3 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v4i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-LABEL: name: extract_vector_elt_0_v4i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...

---
name: extract_vector_elt_0_v5i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v5i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<5 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<5 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v6i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v6i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<6 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<6 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v7i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v7i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<7 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<7 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v8i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v8i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<8 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v16i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v16i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<16 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<16 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_var_v2i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: extract_vector_elt_var_v2i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[COPY1]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...

---
name: extract_vector_elt_var_v8i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK-LABEL: name: extract_vector_elt_var_v8i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s32>), [[COPY1]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...


---
name: extract_vector_elt_0_v2i8_i32

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s8>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v2i16_i32

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i16_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<2 x s16>), [[C]](s32)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s16)
    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(<2 x s16>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v2i1_i32

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s1>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v2i1_i1

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s1>) = G_IMPLICIT_DEF
    %1:_(s1) = G_CONSTANT i1 false
    %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...