test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN

--- |
  define void @or(i32 addrspace(1)* %global0) {ret void}
...
---

name:            or
legalized:       true
regBankSelected: true

# GCN-LABEL: name: or
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
    ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:vgpr(s32) = COPY $vgpr0
    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %4:sgpr(s32) = G_CONSTANT i32 1
    %5:sgpr(s32) = G_CONSTANT i32 4096

    ; or ss
    ; GCN: [[SS:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[SGPR0]], [[SGPR1]]
    %6:sgpr(s32) = G_OR %0, %1

    ; or vs
    ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VGPR0]]
    %7:vgpr(s32) = G_OR %2, %6

    ; or sv
    ; GCN: [[SV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VS]]
    %8:vgpr(s32) = G_OR %6, %7

    ; or vv
    ; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SV]], [[VGPR0]]
    %9:vgpr(s32) = G_OR %8, %2

    G_STORE %9, %3 :: (store 4 into %ir.global0, addrspace 1)

...
---