test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

  define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
  define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
  define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}

...
---
name:            load_store_i8
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: load_store_i8
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY1]], 0 :: (load 1 from %ir.py)
    ; MIPS32: SB [[LBu]], [[COPY]], 0 :: (store 1 into %ir.px)
    ; MIPS32: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %4:gprb(s32) = G_LOAD %1(p0) :: (load 1 from %ir.py)
    %3:gprb(s32) = COPY %4(s32)
    G_STORE %3(s32), %0(p0) :: (store 1 into %ir.px)
    RetRA

...
---
name:            load_store_i16
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: load_store_i16
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY1]], 0 :: (load 2 from %ir.py)
    ; MIPS32: SH [[LHu]], [[COPY]], 0 :: (store 2 into %ir.px)
    ; MIPS32: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %4:gprb(s32) = G_LOAD %1(p0) :: (load 2 from %ir.py)
    %3:gprb(s32) = COPY %4(s32)
    G_STORE %3(s32), %0(p0) :: (store 2 into %ir.px)
    RetRA

...
---
name:            load_store_i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: load_store_i32
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY1]], 0 :: (load 4 from %ir.py)
    ; MIPS32: SW [[LW]], [[COPY]], 0 :: (store 4 into %ir.px)
    ; MIPS32: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(s32) = G_LOAD %1(p0) :: (load 4 from %ir.py)
    G_STORE %2(s32), %0(p0) :: (store 4 into %ir.px)
    RetRA

...