commit	90801f301f0cb24ae6f8024d434b595a9d8ddd13	[log] [tgz]
author	Nicolas Vasilache <nicolas.vasilache@gmail.com>	Tue Nov 23 12:01:53 2021 +0000
committer	Copybara-Service <copybara-worker@google.com>	Tue Nov 23 05:02:29 2021 -0800
tree	b93bbf03502e0c6c6d6d79917ca36cc8715f0359
parent	89f925cc4a5ffc492caf61006e1f419116b4cac7 [diff]

[mlir][Vector] Thread 0-d vectors through InsertElementOp.

This revision makes concrete use of 0-d vectors to extend the semantics of
InsertElementOp.

Reviewed By: dcaballe, pifon2a

Differential Revision: https://reviews.llvm.org/D114388

GitOrigin-RevId: 3ff4e5f2a4a6a0e124356b2ad8793270ebbb16c1

include/mlir/Dialect/Vector/VectorOps.td[diff]
lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp[diff]
lib/Dialect/Vector/VectorOps.cpp[diff]
test/Conversion/VectorToLLVM/vector-to-llvm.mlir[diff]
test/Dialect/Vector/invalid.mlir[diff]
test/Dialect/Vector/ops.mlir[diff]
test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir[diff]

7 files changed

tree: b93bbf03502e0c6c6d6d79917ca36cc8715f0359

cmake/
docs/
examples/
include/
lib/
python/
test/
tools/
unittests/
utils/
.clang-format
.clang-tidy
CMakeLists.txt
LICENSE.TXT
README.md

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.