commit	89f925cc4a5ffc492caf61006e1f419116b4cac7	[log] [tgz]
author	Nicolas Vasilache <nicolas.vasilache@gmail.com>	Tue Nov 23 12:01:12 2021 +0000
committer	Copybara-Service <copybara-worker@google.com>	Tue Nov 23 04:47:07 2021 -0800
tree	e590008f96e21c70d0e83beba99d72a35bb9ca09
parent	38393c3b1a6208dc8aa38f5d4493d763f7259bb5 [diff]

[mlir][Vector] Thread 0-d vectors through ExtractElementOp.

This revision starts making concrete use of 0-d vectors to extend the semantics of
ExtractElementOp.
In the process a new VectorOfAnyRank Tablegen OpBase.td is added to allow progressive transition to supporting 0-d vectors by gradually opting in.

Differential Revision: https://reviews.llvm.org/D114387

GitOrigin-RevId: e7026aba004934cad5487256601af7690757d09f

include/mlir/Dialect/Vector/VectorOps.td[diff]
include/mlir/IR/OpBase.td[diff]
lib/Conversion/LLVMCommon/TypeConverter.cpp[diff]
lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp[diff]
lib/Dialect/Vector/VectorOps.cpp[diff]
test/Conversion/VectorToLLVM/vector-to-llvm.mlir[diff]
test/Dialect/Vector/invalid.mlir[diff]
test/Dialect/Vector/ops.mlir[diff]
test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir[Added - diff]

9 files changed

tree: e590008f96e21c70d0e83beba99d72a35bb9ca09

cmake/
docs/
examples/
include/
lib/
python/
test/
tools/
unittests/
utils/
.clang-format
.clang-tidy
CMakeLists.txt
LICENSE.TXT
README.md

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.