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llvm / llvm-project / mlir / 73dbbea55584aa3095de97e379e367916fe36ed2
commit73dbbea55584aa3095de97e379e367916fe36ed2[log] [tgz]
authorChristian Ulmann <christianulmann@gmail.com>Thu Apr 18 13:09:16 2024 +0200
committerCopybara-Service <copybara-worker@google.com>Thu Apr 18 04:15:03 2024 -0700
tree5d2c354637905c1563bdd092ace7fa98c4a33ccd
parent90cf2c3315cf9c86d221718f0c44c767c1a9eb96 [diff]
[MLIR][Mem2Reg][LLVM] Enhance partial load support (#89094)

This commit improves LLVM dialect's Mem2Reg interfaces to support
promotions of partial loads from larger memory slots. To support this,
the Mem2Reg interface methods are extended with additional data layout
parameters. The data layout is required to determine type sizes to
produce correct conversion sequences.

Note: There will be additional followups that introduce a similar
functionality for stores, and there are plans to support accesses into
the middle of memory slots.
GitOrigin-RevId: ac39fa740b067f6197dca1caecc97c0da91ebf3d
5 files changed
tree: 5d2c354637905c1563bdd092ace7fa98c4a33ccd
  1. benchmark/
  2. cmake/
  3. docs/
  4. examples/
  5. include/
  6. lib/
  7. python/
  8. test/
  9. tools/
  10. unittests/
  11. utils/
  12. .clang-format
  13. .clang-tidy
  14. CMakeLists.txt
  15. LICENSE.TXT
  16. README.md
README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.