commit	3d23eb8a47a14d661472734b5677de09a546af0a	[log] [tgz]
author	Lei Zhang <antiagainst@google.com>	Mon Nov 22 12:28:39 2021 -0500
committer	Copybara-Service <copybara-worker@google.com>	Mon Nov 22 09:37:21 2021 -0800
tree	b59dcf5a7a7181b9ab1af46ede7d2e159d98e7e7
parent	dd1aab2954d3ecde32c44f2363ddc871c6b9a093 [diff]

[mlir][vector] Fix TransferOpReduceRank for 0-D tensors

We cannot unconditionally generate memref.load ops for such cases;
need to check the source's type.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D114376

GitOrigin-RevId: 93284120f28c82503138f3e594358349ed0ab37f

lib/Dialect/Vector/VectorTransferPermutationMapRewritePatterns.cpp[diff]
test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir[diff]

2 files changed

tree: b59dcf5a7a7181b9ab1af46ede7d2e159d98e7e7

cmake/
docs/
examples/
include/
lib/
python/
test/
tools/
unittests/
utils/
.clang-format
.clang-tidy
CMakeLists.txt
LICENSE.TXT
README.md

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.