| commit | 10ba572cf13af0d161f420b129245ba34d8573e4 | [log] [tgz] |
|---|---|---|
| author | Mogball <jeffniu22@gmail.com> | Thu Nov 18 05:41:25 2021 +0000 |
| committer | Copybara-Service <copybara-worker@google.com> | Thu Nov 18 14:46:14 2021 -0800 |
| tree | eb0fbdd8d0517a840799db9ded16112fe43877ad | |
| parent | 6aed3698cd70a0ee4960eb4376034d188f70c459 [diff] |
[mlir][vector] Insert/extract element can accept index `vector::InsertElementOp` and `vector::ExtractElementOp` have had their `position` operand changed to accept `AnySignlessIntegerOrIndex` for better operability with operations that use `index`, such as affine loops. LLVM's `extractelement` and `insertelement` can also accept `i64`, so lowering directly to these operations without explicitly inserting casts is allowed. SPIRV's equivalent ops can also accept `i64`. Reviewed By: nicolasvasilache, jpienaar Differential Revision: https://reviews.llvm.org/D114139 GitOrigin-RevId: 7c5ecc8b7e1bcd1b02eafeba9bbf3d5bc50d72c5
See https://mlir.llvm.org/ for more information.