)]}' { "log": [ { "commit": "1cc38f520ec85aecd27a4799f91ac580de73e3fb", "tree": "3bd8575d9f913d4c912a4cd1258ad125b9d8ea19", "parents": [ "b565ceecce38b564c951351d53b9db268c159fe5" ], "author": { "name": "paperchalice", "email": "liujunchang97@outlook.com", "time": "Sat Jun 13 17:14:52 2026 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sat Jun 13 02:22:05 2026 -0700" }, "message": "[Passes] Remove redundant IR pass registries in MachinePassRegistry.def (#203659)\n\nIR pass registries are redundant, remove them.\n\nGitOrigin-RevId: 94b46a0ded3aebfa13c0fb63e5637df34a87efbd\n" }, { "commit": "b565ceecce38b564c951351d53b9db268c159fe5", "tree": "0085da93ae49b1d596b9bf11014920315ffadff9", "parents": [ "2bd100f30aa646f6277516875c91bad3f1c98059" ], "author": { "name": "Andrei Safronov", "email": "andrei.safronov@espressif.com", "time": "Sat Jun 13 11:47:05 2026 +0300" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sat Jun 13 01:52:01 2026 -0700" }, "message": "[Xtensa] Implement support of the ESP32S2 target. (#200130)\n\nGitOrigin-RevId: e5cfc1ec130e9ef61fd64369353253f9da894887\n" }, { "commit": "2bd100f30aa646f6277516875c91bad3f1c98059", "tree": "00515cb99a0be48ff21082435a12439d6422ccf7", "parents": [ "4027f635fb2a99a0f16379b36322cd68e7609a7e" ], "author": { "name": "jofrn", "email": "jo7frn1@gmail.com", "time": "Sat Jun 13 01:37:41 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sat Jun 13 01:42:24 2026 -0700" }, "message": "[AtomicExpand][test] Add CHECK32 and CHECK64 via whole-file regen (#201303)\n\nAdd CHECK32 and CHECK64 via whole-file regen for the\n`@load_v2i64_cmpxchg`, `@load_v4i32_cmpxchg`, `@load_v16i8_cmpxchg`\ntests of https://github.com/llvm/llvm-project/pull/199310.\n\nStacked below https://github.com/llvm/llvm-project/pull/199520.\n\nGitOrigin-RevId: 34802b90f3877abb71faf43ff80ffae985ab2672\n" }, { "commit": "4027f635fb2a99a0f16379b36322cd68e7609a7e", "tree": "7bff8171936b79634bf112b14dd87003804719ab", "parents": [ "1935d9dbad36aee3b20552041f76950b5b702d2d" ], "author": { "name": "Aiden Grossman", "email": "aidengrossman@google.com", "time": "Sat Jun 13 08:35:21 2026 +0000" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sat Jun 13 01:41:55 2026 -0700" }, "message": "Reapply \"[lit] Deprecate execute_external\u003dTrue in ShTest\" (#203316) (#203689)\n\nThis reverts commit 6713634507b21efe6c895dd40e85ba72fe0ce269.\n\nThe fuzzer tests now use the internal shell by default, so we should be\ngood to go ahead and enable this.\n\nGitOrigin-RevId: 57109befac92811d2253109242ca6fa69c961fb2\n" }, { "commit": "1935d9dbad36aee3b20552041f76950b5b702d2d", "tree": "06a674c620c29d808964b7a4dbf1ca9d6f297e18", "parents": [ "ea04502347ba3db434b796302411c1b8a6a8c440" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Sat Jun 13 01:31:19 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sat Jun 13 01:37:10 2026 -0700" }, "message": "[AMDGPU] gfx1251 cost model (#203682)\n\nGitOrigin-RevId: cbf3f87d6c950208ed95a5dcf4399b79e7e74baf\n" }, { "commit": "ea04502347ba3db434b796302411c1b8a6a8c440", "tree": "cdfad8de5693c135942ed376494f954ec447b51f", "parents": [ "d9f0fb3df16c28479a02507e95a7f3e04767d89e" ], "author": { "name": "Dmitry Sidorov", "email": "Dmitry.Sidorov@amd.com", "time": "Sat Jun 13 10:23:25 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Sat Jun 13 01:27:27 2026 -0700" }, "message": "[SPIR-V] Preserve pointer-to-pointer element type for T*\u0026 parameters (#203113)\n\nSPIR-V backend was collapsing T*\u0026 reference parameters down to T*,\ndropping a level of indirection during element-type deduction. This\npatch keeps the pointer-to-pointer level intact, fixing it both within a\nfunction (a T** reloaded from its alloca) and across calls via\ncross-function parameter propagation.\n\nFixes HeCBench/topk on HIP.\n\nGitOrigin-RevId: 9a3e91daa7798e8695a68b01a8ff9b76e54f8524\n" }, { "commit": "d9f0fb3df16c28479a02507e95a7f3e04767d89e", "tree": "fae5c5b86fec001ed7a5dcfc11f2a8587aa51f90", "parents": [ "7543ae1af1bf93c9270e22b07dee901ccfa84ff5" ], "author": { "name": "agrieve", "email": "agrieve@chromium.org", "time": "Sat Jun 13 00:01:35 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 21:06:44 2026 -0700" }, "message": "[X86] Disallow immediate address calls when position independent (#202370)\n\nCauses problems with mold linker, and was determined to be a compiler\nbug. See:\nSee https://github.com/rui314/mold/pull/1601#issuecomment-4628653209\n\nGitOrigin-RevId: e5afb8e0982c524ee79436a15fb7270d4b9436f3\n" }, { "commit": "7543ae1af1bf93c9270e22b07dee901ccfa84ff5", "tree": "89cc29b4a6b3da7499489fb07c7f77fe3ef6d12f", "parents": [ "6cbff163b78b02a7d75ca349269c266889618ac0" ], "author": { "name": "Changpeng Fang", "email": "changpeng.fang@amd.com", "time": "Fri Jun 12 19:07:24 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 19:11:47 2026 -0700" }, "message": "[AMDGPU] Add a few wmma co-execution hazard checks, NFC (#203658)\n\nThis is to reflect the gfx1251 update regarding wmma*8f6f4 with\n matrix format as F4.\n\n Also fix a comment in GCNHazardRecognizer.cpp\n\nGitOrigin-RevId: e602cd1acc04bd1a16a21d4d1d2d81037fa306f2\n" }, { "commit": "6cbff163b78b02a7d75ca349269c266889618ac0", "tree": "5c5b8edc7fdb367b5eede188b0e45a6962d00a78", "parents": [ "3b4553e2b191ec16c5040a0342d2d1d10b12fd01" ], "author": { "name": "Alex MacLean", "email": "amaclean@nvidia.com", "time": "Fri Jun 12 19:02:31 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 19:06:51 2026 -0700" }, "message": "[NVPTX] Rip out vestigial variadic support (NFC) (#202385)\n\nGitOrigin-RevId: e63cd40ccce67f9472af9676185d7c87157043b4\n" }, { "commit": "3b4553e2b191ec16c5040a0342d2d1d10b12fd01", "tree": "579244d1d50c334bc1595558e6f01d76ecc81512", "parents": [ "5d50b1e5c38f5f0359792f5d9996797e3e524ccf" ], "author": { "name": "Ilpo Ruotsalainen", "email": "lonewolf@iki.fi", "time": "Fri Jun 12 18:41:36 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 18:47:19 2026 -0700" }, "message": "[GlobalISel] Fix sign-extended byte mask in lowerBswap (#199387)\n\nThe per-byte mask in `LegalizerHelper::lowerBswap` was constructed via\n\n```\nAPInt APMask(SizeInBytes * 8, 0xFF \u003c\u003c (i * 8));\n```\n\nwhere `0xFF \u003c\u003c (i * 8)` is evaluated as a signed `int`. For `i*8 \u003e\u003d 24`\n(byte-3 mask of an s64 G_BSWAP) the value `0xFF000000` does not fit in a\npositive 32-bit `int`; the conversion to signed `int` is\nimplementation-defined under C++17 (UB under C++11, fully defined under\nC++20) and on two\u0027s-complement targets produces `-16777216`. The modular\nconversion to `uint64_t` in the `APInt` constructor then materializes\nthat negative `int` as `0xFFFFFFFFFF000000` — the intended mask was\n`0x00000000FF000000`. The over-wide mask preserved bytes 4-7 of the\nsource where only byte 3 was intended, and the spurious bytes propagated\nthrough the subsequent shift/OR chain.\n\nUse `APInt::getBitsSet` to construct the mask, matching the file\u0027s other\nbit-range mask constructions.\n\nFixes #199386\n\nGitOrigin-RevId: 08e6e1476b4d3273f95ef715391154be0a6881bc\n" }, { "commit": "5d50b1e5c38f5f0359792f5d9996797e3e524ccf", "tree": "bda74c959b4a2fc43894c6ab245ae85628ae1c75", "parents": [ "d0b6f580d5ab357c360350a5b034f8ffc9717d7b" ], "author": { "name": "陈子昂", "email": "2802328816@qq.com", "time": "Sat Jun 13 09:32:10 2026 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 18:37:35 2026 -0700" }, "message": "[VectorCombine] Use TCK_CodeSize for size-optimized functions (#202207)\n\nVectorCombine currently uses `TCK_RecipThroughput` for all functions,\nincluding functions optimized for size.\n\nSelect `TCK_CodeSize` when `Function::hasOptSize()` is true, covering\nboth `-Os` (`optsize`) and `-Oz` (`minsize`), while retaining\n `TCK_RecipThroughput` for the default optimization mode.\n\nThe X86 regression test demonstrates a sign-bit reduction where the\nthroughput cost model folds an `or` reduction into a `umax` reduction.\nThe code-size model preserves the smaller form for `optsize` and\n`minsize` functions, while the default function retains the existing\nthroughput-oriented transformation.\n\n Fixes #153375.\n\nGitOrigin-RevId: afeee229f5160fecf427571141165a4d97c93f00\n" }, { "commit": "d0b6f580d5ab357c360350a5b034f8ffc9717d7b", "tree": "5640771f1bd3efab4887e54fbaf9043f0ac237b5", "parents": [ "7dd6fea59e9b7f1864542edbdd90b359e803b85e" ], "author": { "name": "Craig Topper", "email": "craig.topper@sifive.com", "time": "Fri Jun 12 18:08:45 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 18:12:50 2026 -0700" }, "message": "[RISCV] Add PseudoClearGPR to the special cases in RISCVInstrInfo::getInstSizeInBytes. (#203637)\n\nThis instruction is expanded to an ADDI with immediate of 0 and should\nthen be compressed to c.li with Zca. The compression code doesn\u0027t know\nthis due to the Pseudo so manually give a size of 2 for Zca.\n\nGitOrigin-RevId: e3e2fd630f5969a6ee845a57e3be380331405e2e\n" }, { "commit": "7dd6fea59e9b7f1864542edbdd90b359e803b85e", "tree": "d4d09f2348d4e8d4a1ad586fef6e55f598a35901", "parents": [ "6d302a93c8c38226feb3b341e1615af930890635" ], "author": { "name": "Sergey Stepanov", "email": "23sas32@gmail.com", "time": "Sat Jun 13 02:06:29 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 18:12:16 2026 -0700" }, "message": "[RISCV] Mark HW shadow stack ops as frame setup/destroy (#203362)\n\nThis change follows up on PR #200182 and addresses the issue in the\n[related\ncomment](https://github.com/llvm/llvm-project/pull/200182#discussion_r3329197379).\n\nIt sets `FrameSetup` on SSPUSH/C_SSPUSH and `FrameDestroy` on SSPOPCHK\ninstructions emitted by RISCVFrameLowering for the HW shadow stack path.\nThe test was written manually (instead of using\n`utils/update_mir_test_checks.py`) to keep it simple and avoid\nunnecessary fragility.\n\nGitOrigin-RevId: 4e5fa3bbabdf304975abf9eea59bc44d72277169\n" }, { "commit": "6d302a93c8c38226feb3b341e1615af930890635", "tree": "0db64df2e35fd0b807a208842a9c909fb2ebdbf1", "parents": [ "fa1c72468559e30db22805d017338626491711dc" ], "author": { "name": "Rahul Joshi", "email": "rjoshi@nvidia.com", "time": "Fri Jun 12 16:51:36 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 16:56:59 2026 -0700" }, "message": "[NFC][LLVM] Refactor IIT_ANY payload for vector/element constraint (#203506)\n\nChange `IIT_ANY` payload from a single packed OverloadIndex + AnyKind\nbyte to 2 bytes:\n- An 8 bit OverloadIndex\n- An 8 pit packed vector + element type constraint.\nThis will enable `IIT_ANY` to express constraints on the overload type\nis a more general fashion compared to a flat `AnyKind` enum.\n\nAlso fixed a latent bug in fixed encodings generated by the intrinsic\nemitter (exposed by this change). Existing `encodePacked` packs the\ntype-signature as 8 nibbles into a 32-bit word and then checks if the\nMSB bit position (i.e., bit 15) is 0 (to allow it\u0027s use in fixed\nencoding). This effectively drop any 0 valued bytes in the encoding in\nthe upper 4 nibbles. Fix this by changing `encodePacked` to use the\nactual fixed encoding type and its size.\n\nGitOrigin-RevId: 0579490edf0599cc01e10885c2149d4cce8ec399\n" }, { "commit": "fa1c72468559e30db22805d017338626491711dc", "tree": "a3e1cfe3d54d50b03b6b3f4ab1414fe335e91de7", "parents": [ "5387a30b19b45d678f3e64cd83955650406635b4" ], "author": { "name": "dpalermo", "email": "dan.palermo@amd.com", "time": "Fri Jun 12 16:52:32 2026 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 14:57:53 2026 -0700" }, "message": "Revert \"[AMDGPU] In `LowerDYNAMIC_STACKALLOC`, hoist the `readfirstlane` up one instruction\" (#203645)\n\nReverts llvm/llvm-project#201528\n\nReverting due to change causing \"illegal VGPR to SGPR copy\"\n\nGitOrigin-RevId: 81a81d7fae4a16e0edfdb0273f5c376547e15841\n" }, { "commit": "5387a30b19b45d678f3e64cd83955650406635b4", "tree": "f4732d839364f171fdc3c491ec7f42509651b5ce", "parents": [ "51d4100327c8d1889217e2d00ca376ec81faa74a" ], "author": { "name": "Dmitry Sidorov", "email": "Dmitry.Sidorov@amd.com", "time": "Fri Jun 12 23:38:30 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 14:41:33 2026 -0700" }, "message": "[SPIR-V] Lower freeze instructions with aggregate operands (#203584)\n\nAn aggregate freeze takes its result type from its operand, like a PHI\nor select, but was handled by neither the up-front value-id mutation nor\nreplaceMemInstrUses, so the pass aborted with \"illegal aggregate\nintrinsic user\". Mutate aggregate freezes to the i32 value-id type and\nreplace their operands alongside PHIs and selects.\n\nGitOrigin-RevId: 0a6e0210df5596f4aa35b6d01d0dcedc9414dab9\n" }, { "commit": "51d4100327c8d1889217e2d00ca376ec81faa74a", "tree": "6080155be7b528f5e399d9ee897dc7a08df77a34", "parents": [ "f3680b9f0c7423a367cc6dfe16f92dd4f2ca504e" ], "author": { "name": "Guo Chen", "email": "guochen2@amd.com", "time": "Fri Jun 12 17:10:37 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 14:15:05 2026 -0700" }, "message": "[AMDGPU][true16] extract 16bit for scratch_load_ubyte_st when spilling (#203589)\n\nIn sramecc mode scratch_load_ubyte_st is selected for 16bit spilling.\nNeed a tmp vgpr32 and extract lo16 from it\n\nGitOrigin-RevId: 4c057feb7835680c39c78e826c033307bec74295\n" }, { "commit": "f3680b9f0c7423a367cc6dfe16f92dd4f2ca504e", "tree": "fb82a508d4fe18688d55c820661d501b44ce4466", "parents": [ "38739b37a76b5ac73dbd24ecce7ccfde6a1f6589" ], "author": { "name": "Jon Roelofs", "email": "jonathan_roelofs@apple.com", "time": "Fri Jun 12 14:07:01 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 14:12:58 2026 -0700" }, "message": "[AArch64][PAuth] Fix return-address auth for swifttailcc with FPDiff \u003e 0 (#203340)\n\nWhen a swifttailcc tail call has FPDiff \u003e 0 (the caller received more\nstack argument space than the callee pops), the epilogue contains an SP\nadjustment to discard the leftover argument space. The existing code\ntreated both FPDiff \u003c 0 and FPDiff \u003e 0 uniformly in a single \u0027FPDiff !\u003d\n0\u0027 block, using AUTI[AB]1716 with a reconstructed entry-SP in x16 for\nboth cases.\n\nFor FPDiff \u003c 0 (callee pops more) that reconstruction is necessary and\ncorrect. For FPDiff \u003e 0 it is wrong: by the time we enter the block the\npost-index LDP has already adjusted SP back to the frame base, but the\n\u0027add sp, sp, #N\u0027 argument pop has not yet run. Entry SP equals the\ncurrent SP at that point, so AUTI[AB]SP would work directly, but instead\nthe combined block bumped SP via StackOffset::getFixed(-FPDiff) which\novershoots, and then emits AUTIA1716 with a wrong discriminator. Worse\nyet, the SP restore had already been emitted *before* the auth, leaving\nthe live argument stack below SP and outside the red-zone during the\nauthentication window.\n\nFix by splitting the block on the sign of ArgumentStackToRestore:\n\n* `\u003c 0`: reconstruct entry SP in x16, save LR in x17, authenticate with\nAUTI[AB]1716 (or AUTI[AB]171615 / PACM+AUTI[AB]1716 for PAuthLR).\n\n* `\u003e 0`: temporarily remove the \u0027add sp, sp, #N\u0027 SP-modifying\ninstructions from before the auth instruction (SPMods shuffle),\nauthenticate with AUTI[AB]SP (SP \u003d\u003d entry SP at this point), then\nre-insert the SP adjustment afterward.\n\nGitOrigin-RevId: 181d8084770935e4e3cd1877d317e95b73fe8368\n" }, { "commit": "38739b37a76b5ac73dbd24ecce7ccfde6a1f6589", "tree": "865786d5dc9a614a88a9dfec747df9f0c01f34a9", "parents": [ "a571ada65ef86fc89390f79ae3e070095df70747" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Fri Jun 12 13:56:19 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 14:02:10 2026 -0700" }, "message": "[AMDGPU] Add gfx1251 V_PK_LSHL_ADD_U64 (#203612)\n\nGitOrigin-RevId: 8fb9963fd4da8bc5b3b7e186cd369102f42d3640\n" }, { "commit": "a571ada65ef86fc89390f79ae3e070095df70747", "tree": "fd84d46f603423aef2bd020f03064d3447463d95", "parents": [ "c9b64a4efbd0f916f466568cf08f3b145fa60faa" ], "author": { "name": "Ryotaro Kasuga", "email": "kasuga.ryotaro@fujitsu.com", "time": "Sat Jun 13 05:41:34 2026 +0900" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 13:44:11 2026 -0700" }, "message": "[LoopInterchange] Mark getAddRecCoefficient with static (#203624)\n\nAs this function is a file-scope non-member function, it\u0027s better to\nmark it with static.\n\nGitOrigin-RevId: d0cd530bf4e28732368244476c4f504a4920e6c4\n" }, { "commit": "c9b64a4efbd0f916f466568cf08f3b145fa60faa", "tree": "a00e84328751246b6467b7ac50b51ed9fb3c305d", "parents": [ "8eca9b26c05c200e4d2f438832f7ceedbf2756b7" ], "author": { "name": "Ryotaro Kasuga", "email": "kasuga.ryotaro@fujitsu.com", "time": "Sat Jun 13 05:38:29 2026 +0900" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 13:43:42 2026 -0700" }, "message": "[LoopInterchange] Fix crash when followLCSSA returns constant (#203515)\n\nSimilar as the case in ##201069, `followLCSSA` may return a constant\nvalue, but it was cast to Instruction unconditionally. We need to\nexplicitly check whether the returned value is an Instruction or not.\n\nFix #203375.\n\nGitOrigin-RevId: 2f8a39d73394b9a50a32fed5430896afa32a06f5\n" }, { "commit": "8eca9b26c05c200e4d2f438832f7ceedbf2756b7", "tree": "99974aa5b0f8a30e0680615ec3d7aa72fd5a7a5b", "parents": [ "7d28780bca385cbe656583238057e99941f24f50" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Fri Jun 12 13:36:35 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 13:40:37 2026 -0700" }, "message": "[AMDGPU] Enable S_ADD_PC_I64 on gfx1251 (#203613)\n\nGitOrigin-RevId: ae026a59dad1a0a59209418f7a39e16a889c8ac1\n" }, { "commit": "7d28780bca385cbe656583238057e99941f24f50", "tree": "734f80e5aa845b0e8d5243abeaf14723133400d0", "parents": [ "daec78dbe125c97dbe36b13b3dc55a76f0b578d8" ], "author": { "name": "Alexey Bataev", "email": "a.bataev@outlook.com", "time": "Fri Jun 12 16:33:05 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 13:36:58 2026 -0700" }, "message": "[SLP] Vectorize full insertvalue buildvector sequences\n\nTreat a complete chain of insertvalue instructions building a homogeneous\nliteral struct from scalars as a buildvector, like insertelement sequences.\nThe scalars are vectorized into one vector; the aggregate is rebuilt from it\nvia a stack store + load, or stored directly when its only user is a store.\n\ninsertvalue is routed through the existing insertelement buildvector paths\n(type/index helpers, reordering, tree build, cost model, min-bitwidth, and\ncodegen). Only single-index, non-vector inserts building from an undef\naggregate are handled.\n\nFixes #43353\n\nReviewers: hiraditya, bababuck\n\nPull Request: https://github.com/llvm/llvm-project/pull/200274\n\nGitOrigin-RevId: c4c30cebec281eb52e9742cfb1f892fa3c1d9624\n" }, { "commit": "daec78dbe125c97dbe36b13b3dc55a76f0b578d8", "tree": "39fc6e286bc10ea102e217fba9ced0a8c9c55822", "parents": [ "455f65b2b629d5eda247aa178fdccd831232bfb2" ], "author": { "name": "Jeffrey Byrnes", "email": "jeffrey.byrnes@amd.com", "time": "Fri Jun 12 13:08:15 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 13:18:36 2026 -0700" }, "message": "[AMDGPU] NFC: Drop constexpr from getFlavor*Name functions (#203603)\n\nIt seems specifying these as constexpr was causing some buildbot\nfailures due to llvm_unreachable --\n\n```\n[1/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o\nFAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o\n/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI\u003d1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE\u003d_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror\u003ddate-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std\u003dc++17 -fvisibility\u003dhidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp\nIn file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,\n from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,\n from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.h:20,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h:16,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp:14:\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function \u0027constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)\u0027:\n/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-\u0027constexpr\u0027 function \u0027void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)\u0027\n ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro \u0027llvm_unreachable\u0027\n llvm_unreachable(\"Unknown InstructionFlavor\");\n\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function \u0027constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)\u0027:\n/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-\u0027constexpr\u0027 function \u0027void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)\u0027\n ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro \u0027llvm_unreachable\u0027\n llvm_unreachable(\"Unknown InstructionFlavor\");\n\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function \u0027constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)\u0027:\n/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-\u0027constexpr\u0027 function \u0027void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)\u0027\n ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro \u0027llvm_unreachable\u0027\n llvm_unreachable(\"Unknown AMDGPUSchedReason\");\n\n[2/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o\nFAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o\n/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI\u003d1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE\u003d_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror\u003ddate-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std\u003dc++17 -fvisibility\u003dhidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp\nIn file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,\n from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,\n from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h:17,\n from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:17:\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function \u0027constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)\u0027:\n/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-\u0027constexpr\u0027 function \u0027void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)\u0027\n ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro \u0027llvm_unreachable\u0027\n llvm_unreachable(\"Unknown InstructionFlavor\");\n\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function \u0027constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)\u0027:\n/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-\u0027constexpr\u0027 function \u0027void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)\u0027\n ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro \u0027llvm_unreachable\u0027\n llvm_unreachable(\"Unknown InstructionFlavor\");\n\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function \u0027constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)\u0027:\n/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-\u0027constexpr\u0027 function \u0027void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)\u0027\n ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~\n/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro \u0027llvm_unreachable\u0027\n llvm_unreachable(\"Unknown AMDGPUSchedReason\");\n\nninja: build stopped: subcommand failed.\n```\n\nSee alo\n\n(https://github.com/llvm/llvm-project/pull/192322#issuecomment-4672427400)\n\nGitOrigin-RevId: 87d29e3f438c9c02390a4260e9a1bc7712f882c2\n" }, { "commit": "455f65b2b629d5eda247aa178fdccd831232bfb2", "tree": "2a7b0359fcbbf0f9ba82aea371c2022be0a3712c", "parents": [ "d0620df283cc35d2439a7eb80623598c7a916cd2" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Fri Jun 12 13:06:19 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 13:12:40 2026 -0700" }, "message": "[AMDGPU] Add gfx1251 V_PK_ADD/SUB_NC_U64 (#203607)\n\nGitOrigin-RevId: b312ae01043b75637f4fd4dbaf66a09907f63c22\n" }, { "commit": "d0620df283cc35d2439a7eb80623598c7a916cd2", "tree": "f3fcbefa68f8735f839a0b49e462bb2f581c71c9", "parents": [ "d2eca0d4d37d2c3b53de57f9655d00c5a422f448" ], "author": { "name": "Florian Hahn", "email": "flo@fhahn.com", "time": "Fri Jun 12 22:00:34 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 13:07:28 2026 -0700" }, "message": "[ConstraintElim] Add test with negative offset and NUW only GEP (NFC) (#203614)\n\nAdd test currently mis-compiled with NUW only GEP.\n\nhttps://alive2.llvm.org/ce/z/7G8uE3\n\nGitOrigin-RevId: ce09519f40a6d76ec231ef8e4630c0d85c8cdaa5\n" }, { "commit": "d2eca0d4d37d2c3b53de57f9655d00c5a422f448", "tree": "218ef63bf393a3d60b22da3b4d2ba5159077272c", "parents": [ "da9203ccd21786c5daa6157be8ffe8f4717e9fe6" ], "author": { "name": "Ryan Buchner", "email": "rbuchner@qti.qualcomm.com", "time": "Fri Jun 12 12:50:35 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 12:57:07 2026 -0700" }, "message": "Revert \"[LICM] Allow hoisting of InsertElementInst\u0027s past non-hoistable InsertElementInsts\" (#203611)\n\nReverts llvm/llvm-project#200532\n\nGitOrigin-RevId: 12d95c65fc99a3d5686f1d409572d1965fd653b1\n" }, { "commit": "da9203ccd21786c5daa6157be8ffe8f4717e9fe6", "tree": "6aae51b7f5704282d3d10e7acda15f9ba0b2f60a", "parents": [ "ef36a9f767cc61ff4c1c8fa55e46341d53bbb201" ], "author": { "name": "lijinpei-amd", "email": "jinpli@amd.com", "time": "Sat Jun 13 03:22:06 2026 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 12:27:40 2026 -0700" }, "message": "[llvm-diff] Respect AllowAssumptions in diffCallSites (#203597)\n\ndiffCallSites always built an AssumptionContext, so call sites made\noptimistic equivalence assumptions even when the caller disabled them.\nThis made matchForBlockDiff over-match, and the re-check in unify() then\nhit the \"structural differences second time around?\" assertion.\n\nThread the caller\u0027s AssumptionContext into diffCallSites so call sites\nhonor the no-assumptions request like every other instruction kind.\n\nFixes #184133\n\nGitOrigin-RevId: 0b128394b9c796ebe4efd9e0dde38976fb291798\n" }, { "commit": "ef36a9f767cc61ff4c1c8fa55e46341d53bbb201", "tree": "b2b28cef4cd1b67dec7230b2dcfd72d9cf35111e", "parents": [ "2a28fc2d5c3efc68bfdd6f14132742907c0de357" ], "author": { "name": "Farzon Lotfi", "email": "farzonlotfi@microsoft.com", "time": "Fri Jun 12 15:05:28 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 12:27:02 2026 -0700" }, "message": "[SimplifyCFG][DirectX] Honor target minimum lookup table element width (#203103)\n\nfixes #202481\n\nThis change adds a `TTI::getMinimumLookupTableEntryBitWidth()` (default\n`8`) and fold it\ninto SimplifyCFG\u0027s `NeededBitWidth` computation so targets can prevent\nunsupported\nnarrow lookup tables. DirectX returns 32 (or 16 with native 16-bit\ntypes) so tables\nnever narrow to the unsupported i8 type.\n\n\u003e Assisted by Claude Opus 4.8\n\nGitOrigin-RevId: 1060a6be0a471106fd65a3f16937ee1c588dabed\n" }, { "commit": "2a28fc2d5c3efc68bfdd6f14132742907c0de357", "tree": "8cdd37f84eeee5df931346fa3c78e0a16c3fac8d", "parents": [ "143bb483aef4cd44b56d3cdb98a5568a49e13f5d" ], "author": { "name": "Florian Hahn", "email": "flo@fhahn.com", "time": "Fri Jun 12 21:04:23 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 12:07:34 2026 -0700" }, "message": "[VPlan] Compute URem via APInt in materializeVectorTripCount (#203604)\n\nmaterializeVectorTripCount has a shortcut for scalable steps: if the\nconstant trip count is divisible by the maximum possible runtime step,\nthe vector trip count equals the trip count directly. This called\nAPInt::getZExtValue unconditionally, which asserts when the constant\nvalue needs more than 64 bits.\n\nCompute the URem in APInt to fix the crash.\n\nGitOrigin-RevId: 2c1b71af78df9d7c22e225069971d3276d91d546\n" }, { "commit": "143bb483aef4cd44b56d3cdb98a5568a49e13f5d", "tree": "bafe51fc46553ed7d4265526171be32975dd7ab9", "parents": [ "cc91c07d484fcd0f4c043602ead973b7b730eed3" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Fri Jun 12 11:47:11 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 11:51:47 2026 -0700" }, "message": "[AMGDPU] Add gfx1251 V_PK_MIN/MAX_NUM_F64 (#203596)\n\nAlso legalizes v2f64 fcanonicalize.\n\nGitOrigin-RevId: fda7a72af7a76ac6b51a8a1b1222f878d76405ed\n" }, { "commit": "cc91c07d484fcd0f4c043602ead973b7b730eed3", "tree": "0bd9505a89c0d6325cde6ae484102b38540a79e0", "parents": [ "492c6f7a48804771483eaa954f0572871d10f91a" ], "author": { "name": "Florian Hahn", "email": "flo@fhahn.com", "time": "Fri Jun 12 20:39:05 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 11:42:14 2026 -0700" }, "message": "[VPlan] Introduce m_SelectLike and use to support 2-operand blends. (#194729)\n\nWe should be able to treat 2-operand blends like select by most VPlan\ncode. Add a new m_SelectLike matcher and use in places that only use the\nmatcher to extract operands.\n\nOverall this leads to a small number of improvements in RISCV (~10 files\nchanged in a large IR corpus) and 2 loops changed on AArch64 with\ntail-folding forced.\n\nPR: https://github.com/llvm/llvm-project/pull/194729\nGitOrigin-RevId: 64381998961b4b9324ab5a6f6015b285b59d6bb6\n" }, { "commit": "492c6f7a48804771483eaa954f0572871d10f91a", "tree": "e6ca6f926475dc1204b53bff0bca454427e923c0", "parents": [ "483e62e662a5350ca5e95a21995d6b4b8cfc405d" ], "author": { "name": "Vitaly Buka", "email": "vitalybuka@google.com", "time": "Fri Jun 12 11:21:24 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 11:27:05 2026 -0700" }, "message": "[NFC][Support] Add test for inverted slash-agnostic matching (#203290)\n\nAdd a test case to GlobPatternTest to verify that inverted character\nclasses containing slashes (e.g. [^/] or [^\\\\]) behave correctly\nunder SlashAgnostic mode (i.e. they do not match either slash).\n\nAssisted-by: Gemini\nGitOrigin-RevId: 2a72cd87a5bb9db73708661e8760ff710460ae11\n" }, { "commit": "483e62e662a5350ca5e95a21995d6b4b8cfc405d", "tree": "c94ee15d657711d33fa1f6322a4a1bc22f550d1d", "parents": [ "1b99e331b0135eff52b78fcf529bbe7980b37ade" ], "author": { "name": "Daniel Paoliello", "email": "danpao@microsoft.com", "time": "Fri Jun 12 11:11:19 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 11:18:06 2026 -0700" }, "message": "[llvm-ml] Add MASM unwind v3 support for x64 exception handling and improve MSVC compat (#202809)\n\nNew command-line options:\n- `/unwindv3`: Enable V3 unwind information format\n\nNew MASM directives:\n- `.push2reg` / `.pop2reg`: Push/pop register pairs (PUSH2/POP2)\n- `.beginepilog` / `.endepilog`: Delimit epilog unwind regions\n- `.popreg`, `.freestack`, `.restorereg`, `.restorexmm128`,\n`.unsetframe`: Epilog counterparts of existing prolog directives\n- `.pushframe code`: MASM syntax for interrupt handlers with error codes\n\nNew built-in symbol:\n- `@UnwindVersion`: Returns the current x64 unwind version being used.\n\nError diagnostics:\n- Prolog directives after `.endprolog` are diagnosed\n- Epilog directives outside `.beginepilog`/`.endepilog` are diagnosed\n- Nested `.beginepilog` is diagnosed\n- Unwind v3 directives or using extended registers in directives without\nunwind v3 are diagnosed\n\nGitOrigin-RevId: 5a52d68d6b030b155580ff03f5f8ad0cc9dc2fd9\n" }, { "commit": "1b99e331b0135eff52b78fcf529bbe7980b37ade", "tree": "ea7f9bb2004411f618f51bcac83ea390b5784a4c", "parents": [ "a9987b9c73bbb081acceda8f0736d52225c029d4" ], "author": { "name": "Jiachen Yuan", "email": "jiacheny@nvidia.com", "time": "Fri Jun 12 11:10:44 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 11:17:27 2026 -0700" }, "message": "Reapply \"[ADT] Bitset: add shift operators, word accessors, and etc\" (#195874)\n\nReapplies #193400, which was reverted in #195848 because it broke\nbuildbots with:\n\n```\nBitset.h:271: error: static assertion failed: Unsupported word size\n```\n\nRoot cause: a `static_assert(BitwordBits \u003d\u003d 32, ...)` inside the\ndiscarded `else` branch of `if constexpr (BitwordBits \u003d\u003d 64)` in\n`getWord64()`. The assert\u0027s condition is non-template-dependent\n(`BitwordBits` derives from `sizeof(uintptr_t)`, not from `NumBits`), so\nit is checked even though the branch is discarded, and fires on 64-bit\nhosts. Related:\nhttps://stackoverflow.com/questions/38304847/how-does-a-failed-static-assert-work-in-an-if-constexpr-false-block\n\nFix: drop the redundant inner `static_assert`. The class-level\n`static_assert(BitwordBits \u003d\u003d 64 || BitwordBits \u003d\u003d 32, ...)` already\nenforces the same invariant.\n\nNo functional change beyond the original PR.\n\n---------\n\nCo-authored-by: Rahul Joshi \u003crjoshi@nvidia.com\u003e\nGitOrigin-RevId: 660771d4359b14fe56a5eef19c33f93475aee39e\n" }, { "commit": "a9987b9c73bbb081acceda8f0736d52225c029d4", "tree": "59c7c0cb725163dbe79d47611c0b396d102db454", "parents": [ "5558f3032dc83086ca20cd5969cf7eef71e812d5" ], "author": { "name": "Jiaqi He", "email": "heturing@gmail.com", "time": "Fri Jun 12 11:55:32 2026 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 11:02:48 2026 -0700" }, "message": "[RISC-V] Add newer Linux hwprobe extensions detection (#192761)\n\nGitOrigin-RevId: e4a63425ba266f6027e7d257c9a79141c26aa8d8\n" }, { "commit": "5558f3032dc83086ca20cd5969cf7eef71e812d5", "tree": "211a0c0cc98757285d07cc483962edd270f480e4", "parents": [ "34bf5b69232884dcbcc7fe160c1399e48d1e06ec" ], "author": { "name": "Aiden Grossman", "email": "aidengrossman@google.com", "time": "Fri Jun 12 17:42:41 2026 +0000" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 10:46:54 2026 -0700" }, "message": "[Win][x64] Fix -Wunused-variable (#203591)\n\nBaseEpiFlags is only used in assertions, so mark it maybe_unused to\navoid the warning in release builds.\n\nGitOrigin-RevId: 6dbe068edef96c13930471d602fd5fb876e9da04\n" }, { "commit": "34bf5b69232884dcbcc7fe160c1399e48d1e06ec", "tree": "fd755efa68c4a00fc9d01d100a62c441ec7e0010", "parents": [ "965a580e2cffe3ef025e922355f7619b607bd021" ], "author": { "name": "Nikolas Klauser", "email": "nikolasklauser@berlin.de", "time": "Fri Jun 12 19:18:49 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 10:22:37 2026 -0700" }, "message": "[LVI][ValueTracking] Merge checking whether assumes imply nonnull (#203523)\n\nGitOrigin-RevId: 9240c64f4528064cec31e8875fb891b473f8ca7c\n" }, { "commit": "965a580e2cffe3ef025e922355f7619b607bd021", "tree": "477d83bcd6287ff03c3ff1783fa73e2565be212a", "parents": [ "cca8d695e2c7c3b7d93bea353375cbdd9a48ff97" ], "author": { "name": "Benjamin Maxwell", "email": "benjamin.maxwell@arm.com", "time": "Fri Jun 12 17:46:23 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 09:53:43 2026 -0700" }, "message": "[AArch64] Avoid creating a new generic constant in SelectSMETileSlice (#203344)\n\nThis was creating a new ISD::Constant node during instruction selection,\nwhich may also need lowering (e.g., to a `mov gpr, wzr`). The issue with\nthis is the new constant node will not end up on the instruction\nselection worklist, as the complex pattern executes after the worklist\nhas been prepared. This means the constant will lower directly to an\nimmediate. This issue was hidden in some cases by `getConstant()`\nreturning a pre-existing `ISD::Constant` node already within the\ninstruction selection worklist.\n\nThis patch works around this by directly emitting a `CopyFromReg WZR`\nwithin SelectSMETileSlice, which does not need further instruction\nselection.\n\nFixes #203295\n\nGitOrigin-RevId: 528e6f9a030c4b3bf760807c22c98f17fb582f5f\n" }, { "commit": "cca8d695e2c7c3b7d93bea353375cbdd9a48ff97", "tree": "0a7e6f25e7db1cf88c71843c76aa05201ac201fb", "parents": [ "fc77881cb3d2e82c3877ba1fab9bceebca2ecfc2" ], "author": { "name": "Daniel Paoliello", "email": "danpao@microsoft.com", "time": "Fri Jun 12 09:34:32 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 09:36:36 2026 -0700" }, "message": "[win][x64] Windows x64 unwind v3: Update epilog inheritance per spec clarification (#202778)\n\nThe Windows x64 unwind v3 spec was clarified\n(MicrosoftDocs/cpp-docs#5936) to state that an EPILOG_INFO_V3 record\nwith `NumberOfOps \u003d\u003d 0` inherits its effective fields from the first\n*preceding* descriptor with `NumberOfOps !\u003d 0` (the \"base\"), not the\nimmediately preceding one. Additionally, Flags bits 0 and 1 are no\nlonger inherited; the producer must replicate them so they match the\nbase descriptor.\n\n- Encoder (MCWin64EH.cpp): compare each epilog against the tracked base\ndescriptor, and emit EPILOG_INFO_LARGE in inherited descriptors\u0027 own\nflags byte.\n- Decoder (Win64EH.cpp): track the base index and inherit from it; keep\nthe record\u0027s own flags byte instead of copying the previous record\u0027s.\n- Dumpers (llvm-readobj, llvm-objdump): reword \"previous epilog\" to\n\"base epilog\".\n- Tests: update multi-epilog expectations and add a LARGE\ninherited-epilog case to seh-unwindv3-inheritance.s.\n\nGitOrigin-RevId: 878bbacfb0e6ced7c0313d5f7c097d7c94a1c4da\n" }, { "commit": "fc77881cb3d2e82c3877ba1fab9bceebca2ecfc2", "tree": "5c4859f65d7f29a2fc6e535b89723c927c0b5b75", "parents": [ "4f2378a9d7c991dca8ac8d6006a3a3ef07bf377b" ], "author": { "name": "Quentin", "email": "qcoelho@nvidia.com", "time": "Fri Jun 12 09:29:01 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 09:31:48 2026 -0700" }, "message": "[ADT][NFC] Fix documentation for arrayRefFromStringRef (#203430)\n\nThe documentation was describing the opposite behavior of what it does.\n\nGitOrigin-RevId: 99a37aedebd7c69680e74ac83769a11eaefef1e7\n" }, { "commit": "4f2378a9d7c991dca8ac8d6006a3a3ef07bf377b", "tree": "be4bf7a03d0aca90f3d7630e686a8f79429c9784", "parents": [ "748b8845dfe67b7c029216164fa493a445210f70" ], "author": { "name": "dibrinsofor", "email": "64705019+dibrinsofor@users.noreply.github.com", "time": "Fri Jun 12 09:55:08 2026 -0600" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 09:02:44 2026 -0700" }, "message": "[AArch64] Optimize vector slide shuffles with zeros to use shift instructions (#185170)\n\nWe currently emit `movi`+`ext` instructions when generating code for\nshuffle slides of a 64-bit vector left/right and fill it with zeros.\nThis patch optimizes these patterns to use a single `ushr`/`shl`\ninstruction instead.\n\nExample:\n```llvm\n define \u003c8 x i8\u003e @slide_left(\u003c8 x i8\u003e %v) {\n %r \u003d shufflevector \u003c8 x i8\u003e %v, \u003c8 x i8\u003e zeroinitializer,\n \u003c8 x i32\u003e \u003ci32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8\u003e\n ret \u003c8 x i8\u003e %r\n }\n```\n\nBefore, we generate:\n```\n movi v1.2d, #0\n ext v0.8b, v0.8b, v1.8b, #1\n```\n\nNow:\n```\n ushr d0, d0, #8\n```\n\nFixes: #183398\nAlive2 proof: https://alive2.llvm.org/ce/z/QaW5CQ\n\n---------\n\nSigned-off-by: Dibri Nsofor \u003cdibrinsofor@gmail.com\u003e\nGitOrigin-RevId: 9bbed741e260753de029fcf7b22844fe23362a39\n" }, { "commit": "748b8845dfe67b7c029216164fa493a445210f70", "tree": "7fe008d033e3c973f44290bc3a5e73e0b4e0ffa6", "parents": [ "2c72677f9201810c6600175e8804569e57b8d48c" ], "author": { "name": "Jonathan Thackray", "email": "jonathan.thackray@arm.com", "time": "Fri Jun 12 16:47:16 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 08:50:04 2026 -0700" }, "message": "[AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (#187046)\n\nAdd support for the following Armv9.7-A Lookup Table (lut)\ninstruction intrinsics, as defined in the ACLE[1]:\n\nSVE2.3:\n```c\n // Variants are also available for: _u8 _mf8\n svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);\n```\n\nSVE2.3 and SME2.3:\n``` c\n // Variants are also available for _u16_x2 and _f16_x2.\n svint16_t svluti6_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx);\n```\n\nSME2.3:\n```c\n // Variants are also available for: _u16, _f16 and _bf16.\n svint16x4_t svluti6_lane_s16_x4[_s16_x2](svint16x2_t table, svuint8x2_t indices, uint64_t imm_idx);\n\n // Variants are also available for: _u8 and _mf8.\n svint8x4_t svluti6_zt_s8_x4(uint64_t zt0, svuint8x3_t zn) __arm_streaming __arm_in(\"zt0\");\n\n // Variants are also available for: _u8 and _mf8.\n svint8_t svluti6_zt_s8(uint64_t zt0, svuint8_t zn) __arm_streaming __arm_in(\"zt0\");\n```\n\n[1] https://github.com/ARM-software/acle/pull/428/\n\nGitOrigin-RevId: 7814cc9454cf454acdc7385fc41809a6bdf5d7f8\n" }, { "commit": "2c72677f9201810c6600175e8804569e57b8d48c", "tree": "9b3f6a461ed5d6e338085e150d9deb6cf0ace667", "parents": [ "4a3b856419e78d2f0428cdc3467b09b2951bf2f7" ], "author": { "name": "Mikołaj Piróg", "email": "mikolaj.maciej.pirog@intel.com", "time": "Fri Jun 12 17:46:15 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 08:49:39 2026 -0700" }, "message": "[StackColoring] Cleanup stack-coloring test (NFC) (#203551)\n\nThis simply applies postcommit suggestions made here:\nhttps://github.com/llvm/llvm-project/pull/199959\n\nGitOrigin-RevId: 1b774ab021698428374815fb8d4d88855c3b2a48\n" }, { "commit": "4a3b856419e78d2f0428cdc3467b09b2951bf2f7", "tree": "364f6b1a6ad26533b9c9340f905c8a4ff1c46b92", "parents": [ "ef15a48650cc986a1315fc0b2a8b58e87d4f2735" ], "author": { "name": "Quentin Colombet", "email": "quentin.colombet@gmail.com", "time": "Fri Jun 12 17:42:21 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 08:44:42 2026 -0700" }, "message": "[MIR] Save internal VirtRegMap state in MIR (#197361)\n\nAdds two optional fields to the per-vreg YAML record so MIR tests can\nexpress VirtRegMap state that previously had no representation:\n\n registers:\n - { id: 1, class: vgpr_32, split-from: \u0027%0\u0027, assigned-phys: \u0027$vgpr5\u0027 }\n\nTesting passes that consume sibling-register information (e.g.\nInlineSpiller) requires constructing a VirtRegMap with split\nrelationships from a MIR test, which implies triggering live-range\nsplitting at minimum and make reproducers unnecessarily complicated.\n\nSo this change introduces a mechanism to serialize/deserialize the state\nof the VirtRegMap pass.\n\nMechanism:\n- For serialization:\n - MIRPrinter emits the new fields only when the VirtRegMap is available.\n- For deserialization:\n - MIRParser stashes parsed entries in the MachineRegisterInfo object\n - VirtRegMap::init() drains the stash via assignVirt2Phys and\n setIsSplitFromReg, then clears it.\n\nValidation at parse time:\n - \u0027assigned-phys\u0027 must be a physical register.\n - \u0027split-from\u0027 must reference a different vreg than \u0027id\u0027.\n - \u0027split-from\u0027 physregs / named-vreg references already rejected\n by parseStandaloneVirtualRegister.\n\nI\u0027m not super happy about stashing the VRM info in the MRI, but that\u0027s\na small price to pay.\n\nGitOrigin-RevId: 422af7cca672a717bd9505a486e287fa2734bbc9\n" }, { "commit": "ef15a48650cc986a1315fc0b2a8b58e87d4f2735", "tree": "afde237311bc87b0c04bc06485f815a04dc9ce2e", "parents": [ "50ebe061059c106473c0075f325b289d18d6adfb" ], "author": { "name": "Nikita Popov", "email": "npopov@redhat.com", "time": "Fri Jun 12 17:36:47 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 08:42:06 2026 -0700" }, "message": "[IR] Make CanBeFreed calculation optional (NFC) (#203490)\n\nMake the CanBeFreed argument of getPointerDereferenceableBytes() a\npointer, so that nullptr can be passed if we\u0027re not interested in\nwhether frees are possible or not.\n\nNearly all places don\u0027t actually care about frees, including BasicAA,\nwhich is the hottest caller of this API. This improves compile-time when\nderef-at-point semantics are enabled.\n\nI\u0027ve kept the argument required so that callers still have to make an\nexplicit choice to ignore frees. (I\u0027d be open to making it optional\nthough, given that only a single caller actually cares...)\n\nGitOrigin-RevId: 168666950ea9cd85471053319e216399e9750028\n" }, { "commit": "50ebe061059c106473c0075f325b289d18d6adfb", "tree": "0508c41d1fab34e7a10ab8af732c9e36fda639ca", "parents": [ "8fbe3452798f1f87e7184c637515f139d4669a7c" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Fri Jun 12 16:25:02 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 08:31:39 2026 -0700" }, "message": "[X86] combineConcatVectorOps - concat(rotate(x,a),rotate(y,b)) -\u003e rotate(concat(x,y),concat(a,b)) (#203553)\n\n128/256-bit rotates are widened in tablegen, we don\u0027t need to limit\nthese to VLX targets - any AVX512 target can perform these\n\nWe already have test coverage to ensure 128-bit XOP rotates don\u0027t get\nconcatenated to 256-bit\n\nGitOrigin-RevId: 8d2661b2d54e9dec96cba72ff5089c6fa7482bf3\n" }, { "commit": "8fbe3452798f1f87e7184c637515f139d4669a7c", "tree": "00ebb3136506f26da27db88a1f8543dded4792ab", "parents": [ "4451fab1df8c643d0ca9a5676cd2f7f38b27965f" ], "author": { "name": "vangthao95", "email": "vang.thao@amd.com", "time": "Fri Jun 12 08:08:21 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 08:11:47 2026 -0700" }, "message": "AMDGPU/GlobalISel: RegBankLegalize rules for sched barriers intrinsics (#203425)\n\nAdd rules for sched barrier intrinsics. Note, there are regressions due\nto AGPR results being copied back to VGPR un-necessarily. That will be\naddressed in a future follow-up patch.\n\nGitOrigin-RevId: c3a146a4e8fab800c621acc401dbdf1d0c960be8\n" }, { "commit": "4451fab1df8c643d0ca9a5676cd2f7f38b27965f", "tree": "ccba0d4c1b64b1a2d9ebbb6e9a9319c885f7742c", "parents": [ "6ccc13f4a0e902a1021a2f29fa9671d19fbf6c3d" ], "author": { "name": "anjenner", "email": "161845516+anjenner@users.noreply.github.com", "time": "Fri Jun 12 15:56:08 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 08:02:28 2026 -0700" }, "message": "[AMDGPU][GISel] Add register bank legalization rules for amdgcn_cvt_sr_f16_f32. (#203253)\n\nGitOrigin-RevId: 6c3d7edcfa4a266681f19e6a002766c5a7066e34\n" }, { "commit": "6ccc13f4a0e902a1021a2f29fa9671d19fbf6c3d", "tree": "7290cc8459ca750e5771a7b47a87fb1df6cb42ee", "parents": [ "55cfd77e39c5161beb4377732e19fca29512f5b0" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:37:14 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:42:33 2026 -0700" }, "message": "[gn] port 127a4c1a883d333 (LLVM_TARGETS_TO_BUILD for lldb shell tests) (#203547)\n\nGitOrigin-RevId: 09e3e004c66bea58525385486ab04327a51af9de\n" }, { "commit": "55cfd77e39c5161beb4377732e19fca29512f5b0", "tree": "6c259d0ffa680bd0cd48dc10342044affddde2a5", "parents": [ "77e6e8e237ea7d4244ca1b4311c075c02eb91dbb" ], "author": { "name": "Drew Kersnar", "email": "dkersnar@nvidia.com", "time": "Fri Jun 12 09:35:28 2026 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:39:42 2026 -0700" }, "message": "[Bitcode] Decode small byte constants as signed values (#203408)\n\nDecode small byte constants the same way we encode them. The bitcode\nwriter stores ConstantByte values as signed integers, so the reader must\nrebuild them using the signed ConstantByte::get path. This has high-bit\nvalues like b8 255 round-trip as their canonical signed form, b8 -1,\ninstead of tripping the APInt width assertion. This matches current i8\nbehavior.\n\nBefore the fix, the new test crashes in llvm-dis with: \"APInt.h:\nAssertion `llvm::isUIntN(BitWidth, val) \u0026\u0026 \"Value is not an N-bit\nunsigned value\"\u0027 failed.\"\n\nBug found while investigating this PR\n(https://github.com/llvm/llvm-project/pull/177908), which transitions\nthe LSV to emitting the byte type. Fix assisted by AI.\n\nGitOrigin-RevId: 3255d4d7628719c4b6254db5780ec50862584896\n" }, { "commit": "77e6e8e237ea7d4244ca1b4311c075c02eb91dbb", "tree": "5933b90f36b482b9741cf8a1b3a9b1c9c224a480", "parents": [ "e6f48562defaad5b3b9b30d1dcfbbf02f17cd1e5" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:25:20 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:39:08 2026 -0700" }, "message": "[gn build] Port fc1f754c397b (#203542)\n\nGitOrigin-RevId: 305faf498a4e0b52b40742c927af63ab2082e1a9\n" }, { "commit": "e6f48562defaad5b3b9b30d1dcfbbf02f17cd1e5", "tree": "e8d1069d9ecd4e0fb975a10cb914d5fa6587e7a4", "parents": [ "f32c78229cc0c4b6bdbbb1a243a436edc70d9c43" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:24:51 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:30:35 2026 -0700" }, "message": "[gn build] Port df75b5d458b9 (#203541)\n\nGitOrigin-RevId: 422d559a3a3af94c9e74c098761b110d749e248a\n" }, { "commit": "f32c78229cc0c4b6bdbbb1a243a436edc70d9c43", "tree": "7c5d2875337fb0b9fc67721b13cc8b1c99796dd6", "parents": [ "881efbf64a76a8b242e3af33ae8d9c01e450338c" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:23:37 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:30:04 2026 -0700" }, "message": "[gn build] Port d0a1f86e7890 (#203540)\n\nGitOrigin-RevId: 71ff21aa50f07b0cadb929fe14fafda8b1f8243f\n" }, { "commit": "881efbf64a76a8b242e3af33ae8d9c01e450338c", "tree": "1dec35d835f2072a1d5bc19af5fc346e670ba726", "parents": [ "2f8934d7e4c8be4aed4f01871c1c34cc7a22a59e" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:22:53 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:29:30 2026 -0700" }, "message": "[gn build] Port caea95990515 (#203539)\n\nGitOrigin-RevId: e302e85180ab0601ee564237a8cd75184bef5feb\n" }, { "commit": "2f8934d7e4c8be4aed4f01871c1c34cc7a22a59e", "tree": "1bd291dfebd4ce150068bfd15eaa4d751718cab1", "parents": [ "e5c3c327d4e62bad12da75466b7313f31b8c116e" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:22:10 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:29:00 2026 -0700" }, "message": "[gn build] Port b57c32db810b (#203538)\n\nGitOrigin-RevId: c8711e5db4fbe436a5aeede159e1a3c3eae08bf5\n" }, { "commit": "e5c3c327d4e62bad12da75466b7313f31b8c116e", "tree": "f8740bc26085d60108ec3aa05331da6e90579288", "parents": [ "10a94f5db422f19601963f08e1fc276247df2d17" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:21:43 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:28:30 2026 -0700" }, "message": "[gn build] Port b000f9032911 (#203537)\n\nGitOrigin-RevId: d6ddc21af729fc145477e75ada8621e27e017b4e\n" }, { "commit": "10a94f5db422f19601963f08e1fc276247df2d17", "tree": "c44d4f85ac604973c6777184cb05e2163390d7a6", "parents": [ "ff1ea12be37d1d90ae58a62f3f818e1198a43013" ], "author": { "name": "Nico Weber", "email": "thakis@chromium.org", "time": "Fri Jun 12 10:21:05 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:27:57 2026 -0700" }, "message": "[gn] \"port\" 93e03fc2666e (#203536)\n\nGitOrigin-RevId: ad6449fa73fd27b6d3493ab1999befd272e7fb31\n" }, { "commit": "ff1ea12be37d1d90ae58a62f3f818e1198a43013", "tree": "bf79130f264e92472d6d47a5f1ecc04cbda793af", "parents": [ "762effc0b19f7bfee131135b1ac6d8d29102b5ea" ], "author": { "name": "Marina Taylor", "email": "marina_taylor@apple.com", "time": "Fri Jun 12 15:20:47 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:27:22 2026 -0700" }, "message": "[ValueTracking] Infer non-zero from shr (add nuw A, B), C (#203039)\n\n...if either A or B has a known-one bit at position \u003e\u003d C.\n\nhttps://alive2.llvm.org/ce/z/ELYTjh\n\nThis eliminates null checks in some internal workloads.\n\nAssisted-by: claude\nGitOrigin-RevId: 43dc65d46b54415ea474b0bf0ad8b761444a7ba2\n" }, { "commit": "762effc0b19f7bfee131135b1ac6d8d29102b5ea", "tree": "6471f2b289d37f008a9a7f2bc16724109a9e8c1f", "parents": [ "d9c027e713400f1f06933cef2ad57ab9f2b40a0f" ], "author": { "name": "Dmitry Sidorov", "email": "Dmitry.Sidorov@amd.com", "time": "Fri Jun 12 16:14:52 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:17:45 2026 -0700" }, "message": "[AMDGPU] Fix illegal AGPR reclassification in RewriteMFMAFormStage (#200972)\n\nIf src2 escapes rewrite group then bridge copy AGPR -\u003e VGPR must be\ninserted.\n\nFixes a regression after\nhttps://github.com/llvm/llvm-project/pull/198555\n\nGitOrigin-RevId: 0e704a021a5b9c82ee59d855401ef427385e4af1\n" }, { "commit": "d9c027e713400f1f06933cef2ad57ab9f2b40a0f", "tree": "44faeadb049165ecc61a408aa445e25174b71724", "parents": [ "0745bbdca06f77016f20d1ccaffd0e7ae47fef4e" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Fri Jun 12 15:03:49 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 07:07:27 2026 -0700" }, "message": "[X86] combineConcatVectorOps - concat(roti(x,i),roti(y,i)) -\u003e roti(concat(x,y),i) on non-vlx targets (#203528)\n\n128/256-bit rotates are widened in tablegen, we don\u0027t need to limit\nthese to VLX targets - any AVX512 target can perform these\n\nWe already have test coverage to ensure 128-bit XOP rotates don\u0027t get\nconcatenated to 256-bit\n\nGitOrigin-RevId: daa9ecff7ea3ed9a99fd5b486516495655259971\n" }, { "commit": "0745bbdca06f77016f20d1ccaffd0e7ae47fef4e", "tree": "cf2190cf4ddda7b4781c13ea90b59a9c5efa679d", "parents": [ "3e131870566af51617a868e44f6df6dce688d970" ], "author": { "name": "Arseniy Obolenskiy", "email": "arseniy.obolenskiy@amd.com", "time": "Fri Jun 12 15:40:04 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 06:46:58 2026 -0700" }, "message": "[AMDGPU] Fix copy-paste in hasNon16BitAccesses OpIs16Bit check (#203499)\n\nOpIs16Bit tested TempOtherOp width instead of TempOp, mismatching\nsymmetric OtherOpIs16Bit clause\n\nNo observed miscompiles or direct issues to due to that so far\n\nGitOrigin-RevId: 1badbb2a77f6937c9af84a694e1d949c7952b744\n" }, { "commit": "3e131870566af51617a868e44f6df6dce688d970", "tree": "ba19f0d62d824f106f95f60582a22f41426f8014", "parents": [ "f6a88816c36611c15b8a910c8bab03af8986ac0f" ], "author": { "name": "Yaxun (Sam) Liu", "email": "yaxun.liu@amd.com", "time": "Fri Jun 12 09:24:05 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 06:27:43 2026 -0700" }, "message": "[PGO][HIP] Fix HIP device profile collection and sections emission (#202095)\n\nSeveral related HIP device-PGO fixes:\n\nWindows device collection. HIP rejects a hipMemcpy that reads past the\nbounds\nof a symbol registered with __hipRegisterVar, but device\ndata/counters/names\nlive in merged linker sections. Register a separate shadow for each\ndevice\ndata, counters, and names symbol and copy each one by its exact\nhipGetSymbolSize\nsize; this also lets static TUs with several kernels keep all their\nprofile\ndata. Open the device profile file in binary mode and pass the device\nnames to\nthe correct lprofWriteDataImpl arguments so llvm-profdata can read the\nraw\nprofile. Open the versioned amdhip64_7.dll first, falling back to\namdhip64.dll.\n\nPer-TU sections struct. Clang CodeGen emitted the\n__llvm_profile_sections_\u003cCUID\u003e\nstruct (and its section start/stop references) for any profiling-enabled\ndevice\nTU. A TU with no instrumented device functions then referenced sections\nnothing\npopulates, so the RDC device link failed under --no-undefined (and\nduplicated\n__llvm_prf_nm before per-CUID naming). Move the struct emission from\nCGCUDANV\ninto the InstrProfiling pass, which emits it only when the TU has\nprofile data;\nclang emits only the per-TU names-postfix marker, also making names\nunique per\nTU so RDC builds do not clash.\n\nDynamic-module interceptors. The hipModuleLoad* interceptors live in a\nconstructor-only object in clang_rt.profile_rocm that nothing\nreferences, so the\nlinker drops it and dynamic-module programs collect no device profile.\nWhen\nlinking clang_rt.profile_rocm, emit a force-link reference (-u on ELF,\n-include: on COFF); the constructor self-skips when the program does not\nuse\nhipModuleLoad.\n\nMulti-device profile collection. On Linux, static profile collection\nused to\ntry reading profile data from every visible HIP device. This could fault\nwhen a\ndevice was visible but had not launched the instrumented kernel. Track\nHIP\ndevices that successfully launch kernels, and skip unused devices during\nstatic\nprofile collection. If tracking is not available, keep the old\ncollect-all\nbehavior.\n\nDepends on #201607 (reland HIP offload PGO compiler support and link the\ndevice-profile runtime); that PR must land first.\n\nGitOrigin-RevId: 7c0a3a52cf967da9c41d009fb92453b272d0d04a\n" }, { "commit": "f6a88816c36611c15b8a910c8bab03af8986ac0f", "tree": "0659bb213883c38fccd25991baa089962618ad00", "parents": [ "12a9990a36a030039a5cfe21348df897ab8f046d" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Fri Jun 12 14:22:28 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 06:27:10 2026 -0700" }, "message": "[X86] Add tests showing failure to concat 256-bit rotate nodes on non-vlx targets (#203517)\n\nThese are widened in tablegen, we don\u0027t need to limit these to VLX targets\n\nGitOrigin-RevId: 055ef48e1a98545c7ebb9246bb134fecfcc23cae\n" }, { "commit": "12a9990a36a030039a5cfe21348df897ab8f046d", "tree": "319775ef2a33ad632e76f5ad6178b55c1b64fb5b", "parents": [ "c624e69f9f6f37c5298f4d665e096a07895a9a25" ], "author": { "name": "Nikita Popov", "email": "npopov@redhat.com", "time": "Fri Jun 12 14:43:59 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:46:39 2026 -0700" }, "message": "[MergeICmps] Perform dereferenceability check with context (#202884)\n\nTo support deref-at-point semantics, we need to check dereferenceability\nwith a context instruction. Currently, MergeICmps does the check for\neach individual load instruction. In this PR, I\u0027m replacing this with a\ncheck for all the loads that are part of a chain after they have been\ncollected, so we do the context-sensitive check only once.\n\nThe choice of context instruction is a bit tricky: Normally, this would\njust be the first block in the chain (the \"entry block\"), but it\u0027s also\npossible for the block to \"do extra work\", in which case it will get\nsplit. If this happens, we should be checking at the splitting point, as\nthe extra work might be freeing the pointer.\n\nAnother question to consider here is whether we need to be concerned\nabout frees at all: After all, the original code will be accessing at\nleast one byte of the two objects, so doesn\u0027t that imply that it wasn\u0027t\nfreed already? This is indeed the case, as long as allocations cannot\nshrink. This is something we currently don\u0027t allow, but I think it\u0027s\nsomething we want to allow, so I\u0027m going with the conservative treatment\nhere.\n\nGitOrigin-RevId: f77a290a2ffeda2a9974e87fa9120044de0ed93f\n" }, { "commit": "c624e69f9f6f37c5298f4d665e096a07895a9a25", "tree": "9666d5c0761057315110d964284fa4e31d843939", "parents": [ "0ce732a15afecc16bfecbed626e6e45788b95b69" ], "author": { "name": "Harald van Dijk", "email": "hdijk@accesssoftek.com", "time": "Fri Jun 12 13:39:10 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:43:32 2026 -0700" }, "message": "[DirectX] Lower DbgAssign to DbgValue (#200267)\n\nDbgAssign is not representable in LLVM 3.7.\n\nGitOrigin-RevId: a4bdf9d6ccdfcd9300164d9d043d74c78b2624cc\n" }, { "commit": "0ce732a15afecc16bfecbed626e6e45788b95b69", "tree": "7bad316a625fe2e3ebd394181fb9ec9a5adad3f9", "parents": [ "d58e43a031873201fe6d8efe3ded9f4ecadd17f8" ], "author": { "name": "Harald van Dijk", "email": "hdijk@accesssoftek.com", "time": "Fri Jun 12 13:38:47 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:42:57 2026 -0700" }, "message": "[DirectX] Drop DICommonBlock metadata (#201948)\n\nDICommonBlock cannot be represented in LLVM 3.7, but it is a scope\nwithin a parent scope, so we can refer to the parent scope instead.\n\nGitOrigin-RevId: fb009c38d86c4a3c5b13b0ea90bbdb7665670096\n" }, { "commit": "d58e43a031873201fe6d8efe3ded9f4ecadd17f8", "tree": "a38518f9fea57b59ecbb5e0a9f2653c1097c493a", "parents": [ "c8d4f0f2e4dcf4102a389ed447b2bbbb7ff1e19f" ], "author": { "name": "Joachim Meyer", "email": "5982050+fodinabor@users.noreply.github.com", "time": "Fri Jun 12 14:14:00 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:20:57 2026 -0700" }, "message": "[lit] Add support for %{s:stem} substitution. (#202885)\n\nIt provides the source file name with the (last) extension removed.\n\nThis is to align with what is available for %t and actually needed\ndownstream.\n\nGitOrigin-RevId: 8f069e7aea7dbf35d87c8a7a700ae6871b831298\n" }, { "commit": "c8d4f0f2e4dcf4102a389ed447b2bbbb7ff1e19f", "tree": "c6714c2c95d12bc3cb61493992e55270f3ae1a70", "parents": [ "465fae0b6579dbfb850e1b6a37cab5fea7c29f79" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Fri Jun 12 13:13:28 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:20:27 2026 -0700" }, "message": "[X86] combineConcatVectorOps - concat(permi(x,imm0),permi(y,imm1)) -\u003e vpermv3(widen(x),m,widen(y)) (#203508)\n\nAdd handling for X86ISD::VPERMI nodes with different immediates -\nfolding to a X86ISD::VPERMV3 instead, replacing a\nINSERT_SUBVECTOR+2xPERMI nodes with a mask load\n\nWe don\u0027t need to concat the source operands - we have other folds that\nwill do this if beneficial - we just rely on (free) implicit widening.\n\nGitOrigin-RevId: 2b4e89bc254dab3f18b59cd275519d256267b88e\n" }, { "commit": "465fae0b6579dbfb850e1b6a37cab5fea7c29f79", "tree": "13b1c4d85bef3a6727eef8a6ede14d6489e386c7", "parents": [ "5b80f8d7d18f1b0cac8007743ae6715f5edfe901" ], "author": { "name": "Paul Walker", "email": "paul.walker@arm.com", "time": "Fri Jun 12 12:02:01 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:19:53 2026 -0700" }, "message": "[SVE] Replace unnecessary Intrinsic::aarch64_sve_ptrue construction. (#203349)\n\nPrefer ConstantInt::getTrue() over sve.ptrue(31) when creating\nall-active boolean vectors.\n\nGitOrigin-RevId: 663bcb3574d72552b41de6a740e454f2f53e2f4a\n" }, { "commit": "5b80f8d7d18f1b0cac8007743ae6715f5edfe901", "tree": "a31ff80d0056eea2ce28f567735ce374f962c0dd", "parents": [ "b69a7176cf31df8e8e337af3235ce245900ad1f5" ], "author": { "name": "Diego Novillo", "email": "dnovillo@nvidia.com", "time": "Fri Jun 12 06:59:07 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:19:21 2026 -0700" }, "message": "Emit debug type vector (#200056)\n\nThis emits `DebugTypeVector` for HLSL `float4`-style vectors.\n\n`partitionTypes()` separates vector `DICompositeType` nodes from basic\ntypes so both can be visited in a single pass over the debug metadata. A\nnew `emitDebugTypeVector()` helper builds the `DebugTypeVector`\ninstruction and looks up the base-type register in `DebugTypeRegs`.\n\nThe helper skips four cases silently:\n\n1. Absent or non-`DIBasicType` base type: only scalar element types are\nsupported for now.\n2. Base type not yet emitted: the type was not reached during the\n`DebugTypeBasic` pass.\n3. Multiple subranges: `DebugTypeVector` models one-dimensional vectors\nonly (NSDI cannot encode multi-subrange types).\n4. Non-constant subrange count: NSDI cannot represent variable-length\ncounts.\n\nAdded a new test in\n`test/CodeGen/SPIRV/debug-info/debug-type-vector.ll`.\n\nGitOrigin-RevId: 056b4a71c07ff19e38c5cf475fa31fd1271b460d\n" }, { "commit": "b69a7176cf31df8e8e337af3235ce245900ad1f5", "tree": "d00e562050f719e813163f4a942aadb9cfe266c2", "parents": [ "ed543ef2d91a7e83743edf4f2fa2966e41647bd4" ], "author": { "name": "Jay Foad", "email": "jay.foad@amd.com", "time": "Fri Jun 12 11:51:15 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:18:49 2026 -0700" }, "message": "[AMDGPU] Regenerate cluster ID checks (#203494)\n\nGitOrigin-RevId: 274331053cd6b567a02d7ef8a85adcb403dffcb0\n" }, { "commit": "ed543ef2d91a7e83743edf4f2fa2966e41647bd4", "tree": "c26e38404e8273e5848f63c1802c8dbd79075dce", "parents": [ "e5895e8cf89c05203f513c7c68905557c9872a8d" ], "author": { "name": "Nathan Corbyn", "email": "n_corbyn@apple.com", "time": "Fri Jun 12 11:47:44 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:18:19 2026 -0700" }, "message": "[AArch64](NFC) Introduce unified `isLegalArithImmed()` and `isLegalCmpImmed()` (#203020)\n\nQuick tidy up to factor out some common helpers into\n`AArch64AddressingModes.h`.\n\nGitOrigin-RevId: dbc255bedbf5099f32409d41a77bdf0730f4963a\n" }, { "commit": "e5895e8cf89c05203f513c7c68905557c9872a8d", "tree": "b8f54ceafc190b902cb8561c3d92eb85d3b60d9b", "parents": [ "5feca1db04beb15e2899159ec92bdeba69ee53bd" ], "author": { "name": "lijinpei-amd", "email": "jinpli@amd.com", "time": "Fri Jun 12 18:41:47 2026 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 05:17:46 2026 -0700" }, "message": "[KnownFPClass] Fix canonicalize incorrectly dropping fcNegZero under positive-zero denormal mode (#202268)\n\nThe denormal mode only flushes *denormal* (subnormal) values; -0.0 is\nnot a denormal, and per LangRef canonicalize must conserve the sign of\nzero (canonicalize(-0.0) \u003d\u003d -0.0).\n\nAlive2 (InstCombine fold of canonicalize on a {+/-0, nan} value):\n before (miscompiles -0.0 -\u003e +0.0): https://alive2.llvm.org/ce/z/ZRK-sr\n after (verifies): https://alive2.llvm.org/ce/z/L3tPu3\n\nGitOrigin-RevId: da65d6afe74463745dae9af0ce47f31e4186778e\n" }, { "commit": "5feca1db04beb15e2899159ec92bdeba69ee53bd", "tree": "660c822a9e707880f74d326870b87d8922b25f6a", "parents": [ "4c3cc34cc5b4282b658f61a728c0de2a4f0bcfdb" ], "author": { "name": "ambergorzynski", "email": "120007557+ambergorzynski@users.noreply.github.com", "time": "Fri Jun 12 12:25:57 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 03:31:32 2026 -0700" }, "message": "[AMDGPU][NFC] New tests for uncovered cases in SIInstrInfo.cpp (#200414)\n\nSeveral cases in [the AMDGPU\nbackend](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp)\nare not covered by the existing tests. We are proposing a new set of\ntests to cover these lines.\n\nWe demonstrate that these cases are not covered by showing that no test\nfails when `abort` statements are included. These are removed for the\nfinal PR. You can check the lines of interest in [this\ncommit](https://github.com/llvm/llvm-project/pull/200414/commits/84d4587b784014ace546d23beaf6ed8d703452d3).\n\nGitOrigin-RevId: 4a3946fc690c461417d38b6264a1f7a70f5dd364\n" }, { "commit": "4c3cc34cc5b4282b658f61a728c0de2a4f0bcfdb", "tree": "31a6e5105ca222673d708b8c62d8d49a134162af", "parents": [ "785952a29061e6c141f7f30db03dc90a4db0384e" ], "author": { "name": "Simon Pilgrim", "email": "llvm-dev@redking.me.uk", "time": "Fri Jun 12 11:15:04 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 03:21:49 2026 -0700" }, "message": "[X86] Add test showing failure to concat X86ISD::PERMI nodes with different immediates (#203487)\n\nGitOrigin-RevId: ab5da4b999f862e5b165ac87dd9b90ff162e048b\n" }, { "commit": "785952a29061e6c141f7f30db03dc90a4db0384e", "tree": "b9dc566c570d958203d31ccb78cac6f52cfa63c4", "parents": [ "0b24102135018ea2fce16ec63d79ba52958661aa" ], "author": { "name": "Paul Walker", "email": "paul.walker@arm.com", "time": "Fri Jun 12 11:09:38 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 03:12:04 2026 -0700" }, "message": "[LLVM][CodeGen][SPIRV] Match NULL splat to OpConstantNull. (#201313)\n\nGitOrigin-RevId: 125242eb15b6b74e8ad6ab81a760ef4c1b2deea7\n" }, { "commit": "0b24102135018ea2fce16ec63d79ba52958661aa", "tree": "79f545729af3ef69a9594e9bbf5be480023d2e6d", "parents": [ "7ad46f1bae9a01697e2f2173c0c6defebbecae65" ], "author": { "name": "Konstantin Belochapka", "email": "konstantin.belochapka@sony.com", "time": "Fri Jun 12 02:49:29 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:52:11 2026 -0700" }, "message": "[DTLTO] Added missing timetrace \"Check cache for DTLTO\" message. (#203215)\n\nAfter the DTLTO refactor commit, the time trace \"Chack cache for DTLTO\"\nmessage was unintentionally omitted. This patch corrects this omission.\n\nGitOrigin-RevId: 1727b22f5ab476db6b67ff93d5eaf1187e0ecc29\n" }, { "commit": "7ad46f1bae9a01697e2f2173c0c6defebbecae65", "tree": "835f5ead0fb6d5124ac79a844706dd800a816cd6", "parents": [ "b77113eef5d74a3c49ed7b665942a9a12d03431d" ], "author": { "name": "Abhinav Garg", "email": "abhinav.garg@amd.com", "time": "Fri Jun 12 15:14:00 2026 +0530" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:46:41 2026 -0700" }, "message": "[AMDGPU][GlobalIsel] Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD (#192480)\n\nAdd RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD and\nsub-dword variants (UBYTE, SBYTE, USHORT, SSHORT). The lowering covers\nall four rsrc/offset divergence combinations:\n- Uniform rsrc + uniform offset → scalar SMEM (stays as-is)\n- Uniform rsrc + divergent offset → MUBUF (S_BUF_to_BUF, no waterfall)\n- Divergent rsrc + uniform offset → SMEM in waterfall loop over rsrc\n- Divergent rsrc + divergent offset → MUBUF + waterfall over rsrc\n\nTODO:\n1. Fix legalize rule for intrinsic amdgcn_cvt_pkrtz to emit scalar cvt\noperation in _/AMDGPU/scalar-float-sop2.ll_\n2. Fix offset for GFX1250 in\n_/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll_ as done by\nPR#178389\nGitOrigin-RevId: a0bad855ccb86c0ace7be1eb05e51895d61afecc\n" }, { "commit": "b77113eef5d74a3c49ed7b665942a9a12d03431d", "tree": "29874488e147e003f59f07c12fbcf2ce4451624a", "parents": [ "61d90048cfed97d5883a91ee02d215b36b642687" ], "author": { "name": "David Sherwood", "email": "david.sherwood@arm.com", "time": "Fri Jun 12 10:26:07 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:32:04 2026 -0700" }, "message": "[LV] Reland \"Add costs for VPInstructionWithType::computeCost\" (#202952)\n\nThe original change PR #198291 caused a crash due to an unreachable\nopcode. I\u0027ve added support for the missing opcode.\n\nGitOrigin-RevId: ec60d62118bf17328b4d63c67eb981f9c8347d56\n" }, { "commit": "61d90048cfed97d5883a91ee02d215b36b642687", "tree": "f87195e920d04070de22b19c4a40689ac093f2b2", "parents": [ "33ff77d1e38ca02d2189266a25d9976a067d97ab" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@amd.com", "time": "Fri Jun 12 11:07:28 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:12:32 2026 -0700" }, "message": "AMDGPU/GlobalISel: RegBankLegalize rules for gfx950 smfmac intrinsics (#203287)\n\nGitOrigin-RevId: a80153ea4f7dfcd6e0dcf2b415f9ace3cd54015a\n" }, { "commit": "33ff77d1e38ca02d2189266a25d9976a067d97ab", "tree": "404192d58a7824a6c86f975e865629080290706d", "parents": [ "d0fc6c5a36f1122aae65e5046d903ddf396fc8c8" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@amd.com", "time": "Fri Jun 12 11:05:10 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:12:05 2026 -0700" }, "message": "AMDGPU/GlobalISel: RegBankLegalize rules for G_PREFETCH (#203265)\n\nGitOrigin-RevId: 03afb2a0d6becb394901328f051ee9452fb66057\n" }, { "commit": "d0fc6c5a36f1122aae65e5046d903ddf396fc8c8", "tree": "1c254136dae25bf6c768c3c247f2331a369ef27b", "parents": [ "406d1334a0129a3fde570adb25cb8926efaff1f4" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@amd.com", "time": "Fri Jun 12 11:03:46 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:08:59 2026 -0700" }, "message": "AMDGPU/GlobalISel: RegBankLegalize rules for global_load_async_lds (#203280)\n\nGitOrigin-RevId: 81e9fa8d82fd2b6277362c9f27f25ffd24723cb0\n" }, { "commit": "406d1334a0129a3fde570adb25cb8926efaff1f4", "tree": "a0c02afe30bdb05f78e65e706d26d7fa9cfa4d85", "parents": [ "2a3b2abcce212dcb69ce59fc91e7f49c8c6c438d" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@amd.com", "time": "Fri Jun 12 11:02:34 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:08:29 2026 -0700" }, "message": "AMDGPU/GlobalISel: RegBankLegalize rules for load_to_lds intrinsic (#203282)\n\nGitOrigin-RevId: 2e7e9c112d320d1ad032a14621c68b6b5c69a519\n" }, { "commit": "2a3b2abcce212dcb69ce59fc91e7f49c8c6c438d", "tree": "b0cdcd269a41f1cf629d388c04bfb50c72f896d6", "parents": [ "da2cd7f0cca0d119d029d54ea7d4f3e2bc1e66a9" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@amd.com", "time": "Fri Jun 12 11:00:35 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 02:08:01 2026 -0700" }, "message": "AMDGPU/GlobalISel: RegBankLegalize rules for init_whole_wave intrinsic (#203286)\n\nGitOrigin-RevId: 7acd9402f2dbf57e56703ccc2e2b97f51cc7e9dc\n" }, { "commit": "da2cd7f0cca0d119d029d54ea7d4f3e2bc1e66a9", "tree": "12213d5962fd7b9ebaab89c1335d27e2a1925521", "parents": [ "94eb133f0358bac1d6934a119dfdc9b352115ead" ], "author": { "name": "Arseniy Obolenskiy", "email": "arseniy.obolenskiy@amd.com", "time": "Fri Jun 12 10:44:26 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 01:47:40 2026 -0700" }, "message": "[SPIR-V] Replace custom bitcast in FPMaxError decoration handling (NFC) (#203179)\n\nGitOrigin-RevId: 90ca88b509d5c70e98002bde45453877a404ffc8\n" }, { "commit": "94eb133f0358bac1d6934a119dfdc9b352115ead", "tree": "dec89bc602d105fa72ba837a8453aea8b61598e4", "parents": [ "e566d55b49ae3c59a34f611ee9617ae8bb9b9849" ], "author": { "name": "Arseniy Obolenskiy", "email": "arseniy.obolenskiy@amd.com", "time": "Fri Jun 12 10:43:12 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 01:47:15 2026 -0700" }, "message": "[SPIR-V] Merge duplicate case bodies in addInstrRequirements (NFC) (#203177)\n\nGitOrigin-RevId: 15a37869a788864e6d12e805dd0de2dc07a0d764\n" }, { "commit": "e566d55b49ae3c59a34f611ee9617ae8bb9b9849", "tree": "edd3cb67369ae406585005ce56b2d3057b1f6dbe", "parents": [ "fb0a0db56328d03b7d2084e0842b35877e50d84d" ], "author": { "name": "Piotr Sobczak", "email": "piotr.sobczak@amd.com", "time": "Fri Jun 12 10:41:37 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 01:46:48 2026 -0700" }, "message": "[AMDGPU][NFC] Simplify assertions (#203472)\n\nReplace assertions that listed concrete types with generic ones that\ncheck that the type is a vector with an even number of elements.\n\nThis keeps the spirit of the assertions and matches the code.\n\nGitOrigin-RevId: 6a8ad9d1b5c2efc07899796d41956761bd4247b8\n" }, { "commit": "fb0a0db56328d03b7d2084e0842b35877e50d84d", "tree": "d54f7370f946e5052ef65887176ed493e0614bd6", "parents": [ "d2c610f3629c636bba72572e19a3a57ba212885b" ], "author": { "name": "David Sherwood", "email": "david.sherwood@arm.com", "time": "Fri Jun 12 09:36:15 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 01:42:08 2026 -0700" }, "message": "[LV][NFC] Regenerate some CHECK lines (#203343)\n\nGitOrigin-RevId: ce7dae3727322304712f6a1bcdebb254cad9ee60\n" }, { "commit": "d2c610f3629c636bba72572e19a3a57ba212885b", "tree": "d7d1570d8fccefa262b213f8687fd1736df62bac", "parents": [ "e38434187ef0faca66a3ac91bb95049f3dcd030e" ], "author": { "name": "David Green", "email": "david.green@arm.com", "time": "Fri Jun 12 09:24:24 2026 +0100" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 01:27:29 2026 -0700" }, "message": "[AArch64] Change f128 costs to 10 * legalization factor. (#202555)\n\nLowering fadd, fsub, fmul, fdiv and frem will produce a libcall,\nsomething that is always difficult to costmodel. This changes the cost\nmodel to 10 to line up with the value we use for other libcalls.\nNon-rthru costs will start to be used when we start producing accurate\nnon-rthru costs in getArithmeticInstrCost.\n\nGitOrigin-RevId: cb098aa073bbb6ce5d5854d402fbb3e9ecbaaca8\n" }, { "commit": "e38434187ef0faca66a3ac91bb95049f3dcd030e", "tree": "2cd0012ad98ba47973f4ec57b371182cb3fc4f03", "parents": [ "c859ed4cf52eda93c9cad3e89782f87fee8bb3a0" ], "author": { "name": "Fan Mo", "email": "w007878@hotmail.com", "time": "Fri Jun 12 03:22:50 2026 -0500" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 01:27:01 2026 -0700" }, "message": "[docs] Kaleidoscope Tutorial Chapter 7 - base class Value* used for AllocaInst for assignment expression (#202101)\n\nEariler in this chapther, the value type of `NamedValues` was changed to\n`AllocaInst*`, and so did all other occurs for example in\n`VariableExprAST` and `ForExprAST`.\n\nhttps://github.com/llvm/llvm-project/blob/6f8a363a483489687597e29b8bda0975e821f188/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst?plain\u003d1#L321-L324\n\nHowever, the newly added assignment expression is still using `Value*`\nas the type for LHS. Although `Value` is the base class of `AllocaInst`\ntherefore the code compiles and works well, it\u0027s better to keep it\nconsistent\n\nGitOrigin-RevId: dbaa5e601ca06a88e66b95b94dc9d2974b1abded\n" }, { "commit": "c859ed4cf52eda93c9cad3e89782f87fee8bb3a0", "tree": "4e52c0436db86b18655ab1cafee227ee07a4db05", "parents": [ "09102de694193b53cf8b63fc595c3beb6659fde3" ], "author": { "name": "Sven van Haastregt", "email": "sven.vanhaastregt@arm.com", "time": "Fri Jun 12 09:37:36 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Fri Jun 12 00:41:52 2026 -0700" }, "message": "[IR] Fix deprecated-enum-enum-conversion C++20 warnings; NFC (#203277)\n\nThis addition of enum values resulted in many warnings of the form\n\n warning: arithmetic between different enumeration types\n \u0027llvm::Value::ValueTy\u0027 and \u0027llvm::Instruction::TermOps\u0027 is\n deprecated\n\nGitOrigin-RevId: fc8d61811e16874575a73df5e919201c903513c9\n" }, { "commit": "09102de694193b53cf8b63fc595c3beb6659fde3", "tree": "308d4f6e671dd5e5ef15b4cc35e95de66e533d4a", "parents": [ "69fd681be7c580ca213a7376e78e0c9fffad8ad0" ], "author": { "name": "Madhur Amilkanthwar", "email": "madhura@nvidia.com", "time": "Fri Jun 12 11:47:30 2026 +0530" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 23:22:03 2026 -0700" }, "message": "[LoopFusion][NFC] Avoid copying fusion candidates per pair (#203461)\n\n`fuseCandidates()` copied both candidates (each holding two\n`SmallVector\u003cInstruction *, 16\u003e`) for every adjacent pair examined, even\npairs rejected by an early continue. Bind them by const reference; they\nare only read before being erased from the list, and performFusion runs\nbefore the erases.\n\nGitOrigin-RevId: 06c7de45221621a0773d125ff7d016df87eb3d62\n" }, { "commit": "69fd681be7c580ca213a7376e78e0c9fffad8ad0", "tree": "e7cd170090fe362148a7bb85bc60f1f9b87c1d4b", "parents": [ "38b0db7c9692ff55df90ff4fd50eac3f4d368ea2" ], "author": { "name": "Madhur Amilkanthwar", "email": "madhura@nvidia.com", "time": "Fri Jun 12 10:12:12 2026 +0530" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 21:47:12 2026 -0700" }, "message": "Reapply \"[LoopUnroll] Support parallel reductions for minmax\" (#201010)\n\nReapplies 1e79ea1f5b3e (#182473) reverted by 56ccbc253150 (#200892). The\nrevert was due to a profcheck failure: prof-verify reported \"select\nannotation missing\" on the combine select createMinMaxOp emits for FP\nfcmp+select min/max.\n\nThis patch fixes it by marking the branch weights of newly inserted\nselects as explicitly unknown.\n\nGitOrigin-RevId: 452f59c8dc30a3bc16c691f5862bc5b39d97319a\n" }, { "commit": "38b0db7c9692ff55df90ff4fd50eac3f4d368ea2", "tree": "85e5802256f672bef049608b5e0ea1728bd0ec69", "parents": [ "52eb735332bbd408c301aad87ae606e4bf56c52a" ], "author": { "name": "Changpeng Fang", "email": "changpeng.fang@amd.com", "time": "Thu Jun 11 21:03:11 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 21:06:42 2026 -0700" }, "message": "[AMDGPU] Add MC clamp support for bf16 trans instructions (#203433)\n\nBased on recent gfx1250 sp3 update. Refer to DEGFXSP3-664\n\nGitOrigin-RevId: f3f7317aaf39928329dd453a6a340e6ddd027b81\n" }, { "commit": "52eb735332bbd408c301aad87ae606e4bf56c52a", "tree": "0c830fa6358f007fcbe145725ac825e0ab49fdf2", "parents": [ "fcd59a923083c8ab1842876206b7fce1bcf869c6" ], "author": { "name": "Nikolas Klauser", "email": "nikolasklauser@berlin.de", "time": "Fri Jun 12 05:17:46 2026 +0200" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 20:21:28 2026 -0700" }, "message": "[InstCombine] Move noundef assume bundles on loads into metadata (#203395)\n\nGitOrigin-RevId: 0591eef767078a0a079469656658c4a2fc017bbe\n" }, { "commit": "fcd59a923083c8ab1842876206b7fce1bcf869c6", "tree": "44d153ae57211851e4509dc12ee1e3d7f7847a9c", "parents": [ "4a7a79ae03c80de4f76e0c25ce8381ccbf96d93b" ], "author": { "name": "TelGome", "email": "93700071+TelGome@users.noreply.github.com", "time": "Fri Jun 12 10:59:32 2026 +0800" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 20:03:18 2026 -0700" }, "message": "[RISCV][P-ext] Support Packed Averaging Addition and Subtraction intrinsics(#203147)\n\nGitOrigin-RevId: 56f8fbb0149146f50aa8c905467b9384e8cb7bad\n" }, { "commit": "4a7a79ae03c80de4f76e0c25ce8381ccbf96d93b", "tree": "92ab514c345f46bf3ddfcdac9d27dc69518aef44", "parents": [ "22a25f78e5dde3f786033315eae960bc7d7e2520" ], "author": { "name": "David Zbarsky", "email": "dzbarsky@gmail.com", "time": "Thu Jun 11 22:45:09 2026 -0400" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 19:52:44 2026 -0700" }, "message": "[PassBuilder] Table-drive pass name printing (#202656)\n\nReplace the macro-expanded raw_ostream operations in\nPassBuilder::printPassNames with static pass-name arrays and two shared\nnoinline printing loops. Preserve the generated category order and the\nexact spelling of parameterized pass names.\n\nThe change only executes when a client requests the pass-name listing;\nnormal pipeline parsing and optimization do not access the new tables or\nhelpers.\n\nA stripped opt binary shrinks from 115,493,720 to 115,394,640 bytes,\nsaving 99,080 bytes. The linked __TEXT section shrinks by 98,304 bytes.\n\nWork towards #202616\n\nAI tool disclosure: Co-authored with OpenAI Codex.\n\nGitOrigin-RevId: b9704de13ca5ce3158c6681839162a791042c6f9\n" }, { "commit": "22a25f78e5dde3f786033315eae960bc7d7e2520", "tree": "6a49ab4d6fde0a5becf925f8e0c9a8e0023c1602", "parents": [ "721655bce604e403bc934ce0fdf43fa969d54c1e" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Thu Jun 11 19:18:24 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 19:22:30 2026 -0700" }, "message": "[AMDGPU] Make v2f64 fneg legal on gfx1251 (#203427)\n\nGitOrigin-RevId: 8433cf6d6ccc49a0fd99ed86c7d94a1fbb2fd1be\n" }, { "commit": "721655bce604e403bc934ce0fdf43fa969d54c1e", "tree": "4f18ac315be7201c27def48885edf0e5947faf58", "parents": [ "843adec5e1a2dea9bd47ea8e3edb8de36f6adfa8" ], "author": { "name": "Stanislav Mekhanoshin", "email": "Stanislav.Mekhanoshin@amd.com", "time": "Thu Jun 11 16:47:56 2026 -0700" }, "committer": { "name": "Copybara-Service", "email": "copybara-worker@google.com", "time": "Thu Jun 11 16:50:12 2026 -0700" }, "message": "[AMDGPU] Validate WMMA scale/format combination (#203074)\n\nOnly some combinations are listed as supported.\n\nFixes: https://github.com/ROCm/llvm-project/issues/2634\nGitOrigin-RevId: 7597c0c938b364306cbee21dd03835ff5b699c74\n" } ], "next": "843adec5e1a2dea9bd47ea8e3edb8de36f6adfa8" }