tree f8b68947505afb101c047231e62fec1e1505a88c
parent 8154df8e85d7276b9935fdf313dc28e2924b0f06
author Hank Chang <hank.chang@sifive.com> 1758591778 +0800
committer Copybara-Service <copybara-worker@google.com> 1758592093 -0700

[TTI][ASan][RISCV] reland Move InterestingMemoryOperand to Analysis and embed in MemIntrinsicInfo #157863 (#159713)

[Previously reverted due to failures on asan-rvv-intrinsics.ll, the test
case is riscv only and it is triggered by other target]
Reland [#157863](https://github.com/llvm/llvm-project/pull/157863), and
add `; REQUIRES: riscv-registered-target` in test case to skip the
configuration that doesn't register riscv target.

Previously asan considers target intrinsics as black boxes, so asan
could not instrument accurate check. This patch make
SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so
that TTI can make targets describe their intrinsic informations to asan.

Note,
1. This patch move InterestingMemoryOperand from Transforms to Analysis.
2. Extend MemIntrinsicInfo by adding a
SmallVector<InterestingMemoryOperand> member.
3. This patch does not support RVV indexed/segment load/store.

GitOrigin-RevId: f8e51df8e57736d27587baaa5f56e532dfc6de26