test/CodeGen/AMDGPU/coalescer_distribute.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck %s

; This testcase produces a situation with unused value numbers in subregister
; liveranges that get distributed by ConnectedVNInfoEqClasses.

define amdgpu_kernel void @hoge(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) {
; CHECK-LABEL: hoge:
; CHECK:       ; %bb.0: ; %bb
; CHECK-NEXT:    s_load_dword s2, s[4:5], 0x9
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_bitcmp1_b32 s2, 0
; CHECK-NEXT:    s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT:    s_and_b64 s[4:5], s[0:1], vcc
; CHECK-NEXT:    s_and_saveexec_b64 s[0:1], s[4:5]
; CHECK-NEXT:    s_or_b64 exec, exec, s[0:1]
; CHECK-NEXT:    s_bitcmp1_b32 s2, 24
; CHECK-NEXT:    s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT:    s_xor_b64 s[0:1], s[0:1], -1
; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; CHECK-NEXT:    v_cmp_ne_u32_e64 s[0:1], 1, v0
; CHECK-NEXT:  .LBB0_1: ; %bb25
; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT:    s_cbranch_vccnz .LBB0_1
; CHECK-NEXT:  ; %bb.2: ; %bb30
; CHECK-NEXT:    s_endpgm
bb:
  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
  br i1 %c0, label %bb2, label %bb23

bb2:
  br i1 %c1, label %bb6, label %bb8

bb6:
  %tmp7 = or i64 poison, poison
  br label %bb8

bb8:
  %tmp9 = phi i64 [ %tmp7, %bb6 ], [ poison, %bb2 ]
  %tmp10 = icmp eq i32 %tmp, 0
  br i1 %tmp10, label %bb11, label %bb23

bb11:
  br i1 %c2, label %bb20, label %bb17

bb17:
  br label %bb20

bb20:
  %tmp21 = phi i64 [ poison, %bb17 ], [ %tmp9, %bb11 ]
  %tmp22 = trunc i64 %tmp21 to i32
  br label %bb23

bb23:
  %tmp24 = phi i32 [ %tmp22, %bb20 ], [ poison, %bb8 ], [ poison, %bb ]
  br label %bb25

bb25:
  %tmp26 = phi i32 [ %tmp24, %bb23 ], [ poison, %bb25 ]
  br i1 %c3, label %bb25, label %bb30

bb30:
  br i1 %c4, label %bb32, label %bb34

bb32:
  %tmp33 = zext i32 %tmp26 to i64
  br label %bb34

bb34:
  ret void
}

declare i32 @llvm.amdgcn.workitem.id.x()