; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s

define float @test_pown_afn_f32(float %x, i32 %y) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32(
; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[Y]])
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 %y)
  ret float %call
}

declare float @_Z4pownfi(float, i32) #1

define <2 x float> @test_pown_afn_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32(
; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
  ret <2 x float> %call
}

declare <2 x float> @_Z4pownDv2_fDv2_i(<2 x float>, <2 x i32>) #1

define <3 x float> @test_pown_afn_v3f32(<3 x float> %x, <3 x i32> %y) #0 {
; CHECK-LABEL: define <3 x float> @test_pown_afn_v3f32(
; CHECK-SAME: <3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])
; CHECK-NEXT:    ret <3 x float> [[CALL]]
;
entry:
  %call = tail call afn <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)
  ret <3 x float> %call
}

declare <3 x float> @_Z4pownDv3_fDv3_i(<3 x float>, <3 x i32>) #1

define <4 x float> @test_pown_afn_v4f32(<4 x float> %x, <4 x i32> %y) #0 {
; CHECK-LABEL: define <4 x float> @test_pown_afn_v4f32(
; CHECK-SAME: <4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])
; CHECK-NEXT:    ret <4 x float> [[CALL]]
;
entry:
  %call = tail call afn <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)
  ret <4 x float> %call
}

declare <4 x float> @_Z4pownDv4_fDv4_i(<4 x float>, <4 x i32>) #1

define <8 x float> @test_pown_afn_v8f32(<8 x float> %x, <8 x i32> %y) #0 {
; CHECK-LABEL: define <8 x float> @test_pown_afn_v8f32(
; CHECK-SAME: <8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])
; CHECK-NEXT:    ret <8 x float> [[CALL]]
;
entry:
  %call = tail call afn <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)
  ret <8 x float> %call
}

declare <8 x float> @_Z4pownDv8_fDv8_i(<8 x float>, <8 x i32>) #1

define <16 x float> @test_pown_afn_v16f32(<16 x float> %x, <16 x i32> %y) #0 {
; CHECK-LABEL: define <16 x float> @test_pown_afn_v16f32(
; CHECK-SAME: <16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])
; CHECK-NEXT:    ret <16 x float> [[CALL]]
;
entry:
  %call = tail call afn <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)
  ret <16 x float> %call
}

declare <16 x float> @_Z4pownDv16_fDv16_i(<16 x float>, <16 x i32>) #1

define float @test_pown_afn_f32__0(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__0(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret float 1.000000e+00
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 0)
  ret float %call
}

define float @test_pown_afn_f32__1(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__1(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret float [[X]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 1)
  ret float %call
}

define float @test_pown_afn_f32__2(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__2(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
; CHECK-NEXT:    ret float [[__POW2]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 2)
  ret float %call
}

define float @test_pown_afn_f32__3(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__3(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 3)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 3)
  ret float %call
}

define float @test_pown_afn_f32__8(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__8(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 8)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 8)
  ret float %call
}

define float @test_pown_afn_f32__neg1(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__neg1(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POWRECIP:%.*]] = fdiv afn float 1.000000e+00, [[X]]
; CHECK-NEXT:    ret float [[__POWRECIP]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 -1)
  ret float %call
}

define float @test_pown_afn_f32__neg2(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__neg2(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -2)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 -2)
  ret float %call
}

define float @test_pown_afn_f32__neg3(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__neg3(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -3)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 -3)
  ret float %call
}

define float @test_pown_afn_f32__neg8(float %x) #0 {
; CHECK-LABEL: define float @test_pown_afn_f32__neg8(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -8)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call afn float @_Z4pownfi(float %x, i32 -8)
  ret float %call
}

define <2 x float> @test_pown_afn_v2f32__0(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__0(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret <2 x float> splat (float 1.000000e+00)
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> zeroinitializer)
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__1(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__1(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret <2 x float> [[X]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 1))
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__2(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__2(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POW2:%.*]] = fmul afn <2 x float> [[X]], [[X]]
; CHECK-NEXT:    ret <2 x float> [[__POW2]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 2))
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__3(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__3(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 3))
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__8(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__8(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 8))
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 8))
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__neg1(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg1(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POWRECIP:%.*]] = fdiv afn <2 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <2 x float> [[__POWRECIP]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -1))
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__neg2(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg2(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -2))
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__neg3(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg3(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -3))
  ret <2 x float> %call
}

define <2 x float> @test_pown_afn_v2f32__neg8(<2 x float> %x) #0 {
; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg8(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -8))
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -8))
  ret <2 x float> %call
}

define float @test__pown_fast_f32(float %x, i32 %y) #0 {
; CHECK-LABEL: define float @test__pown_fast_f32(
; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z11__pown_fastfi(float [[X]], i32 [[Y]])
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z11__pown_fastfi(float %x, i32 %y)
  ret float %call
}

declare float @_Z11__pown_fastfi(float, i32) #1

define <2 x float> @test__pown_fast_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
; CHECK-LABEL: define <2 x float> @test__pown_fast_v2f32(
; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
  ret <2 x float> %call
}

declare <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float>, <2 x i32>) #1

define <3 x float> @test__pown_fast_v3f32(<3 x float> %x, <3 x i32> %y) #0 {
; CHECK-LABEL: define <3 x float> @test__pown_fast_v3f32(
; CHECK-SAME: <3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])
; CHECK-NEXT:    ret <3 x float> [[CALL]]
;
entry:
  %call = tail call <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)
  ret <3 x float> %call
}

declare <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float>, <3 x i32>) #1

define <4 x float> @test__pown_fast_v4f32(<4 x float> %x, <4 x i32> %y) #0 {
; CHECK-LABEL: define <4 x float> @test__pown_fast_v4f32(
; CHECK-SAME: <4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])
; CHECK-NEXT:    ret <4 x float> [[CALL]]
;
entry:
  %call = tail call <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)
  ret <4 x float> %call
}

declare <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float>, <4 x i32>) #1

define <8 x float> @test__pown_fast_v8f32(<8 x float> %x, <8 x i32> %y) #0 {
; CHECK-LABEL: define <8 x float> @test__pown_fast_v8f32(
; CHECK-SAME: <8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])
; CHECK-NEXT:    ret <8 x float> [[CALL]]
;
entry:
  %call = tail call <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)
  ret <8 x float> %call
}

declare <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float>, <8 x i32>) #1

define <16 x float> @test__pown_fast_v16f32(<16 x float> %x, <16 x i32> %y) #0 {
; CHECK-LABEL: define <16 x float> @test__pown_fast_v16f32(
; CHECK-SAME: <16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])
; CHECK-NEXT:    ret <16 x float> [[CALL]]
;
entry:
  %call = tail call <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)
  ret <16 x float> %call
}

declare <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float>, <16 x i32>) #1

define float @test__pown_fast_f32__0(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_f32__0(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret float 1.000000e+00
;
entry:
  %call = tail call float @_Z11__pown_fastfi(float %x, i32 0)
  ret float %call
}

define float @test__pown_fast_afn_f32__0(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_afn_f32__0(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret float 1.000000e+00
;
entry:
  %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 0)
  ret float %call
}

define float @test__pown_fast_f32__1(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_f32__1(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret float [[X]]
;
entry:
  %call = tail call float @_Z11__pown_fastfi(float %x, i32 1)
  ret float %call
}

define float @test__pown_fast_afn_f32__1(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_afn_f32__1(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    ret float [[X]]
;
entry:
  %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 1)
  ret float %call
}

define float @test__pown_fast_f32__neg1(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_f32__neg1(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POWRECIP:%.*]] = fdiv float 1.000000e+00, [[X]]
; CHECK-NEXT:    ret float [[__POWRECIP]]
;
entry:
  %call = tail call float @_Z11__pown_fastfi(float %x, i32 -1)
  ret float %call
}

define float @test__pown_fast_afn_f32__neg1(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_afn_f32__neg1(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POWRECIP:%.*]] = fdiv afn float 1.000000e+00, [[X]]
; CHECK-NEXT:    ret float [[__POWRECIP]]
;
entry:
  %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 -1)
  ret float %call
}

define float @test__pown_fast_f32__2(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_f32__2(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POW2:%.*]] = fmul float [[X]], [[X]]
; CHECK-NEXT:    ret float [[__POW2]]
;
entry:
  %call = tail call float @_Z11__pown_fastfi(float %x, i32 2)
  ret float %call
}

define float @test__pown_fast_afn_f32__2(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_afn_f32__2(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
; CHECK-NEXT:    ret float [[__POW2]]
;
entry:
  %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 2)
  ret float %call
}

define float @test__pown_fast_f32__neg2(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_f32__neg2(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z11__pown_fastfi(float [[X]], i32 -2)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z11__pown_fastfi(float %x, i32 -2)
  ret float %call
}

define float @test__pown_fast_afn_f32__neg2(float %x) #0 {
; CHECK-LABEL: define float @test__pown_fast_afn_f32__neg2(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.log2.f32(float [[TMP0]])
; CHECK-NEXT:    [[TMP2:%.*]] = fmul afn float [[TMP1]], -2.000000e+00
; CHECK-NEXT:    [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
; CHECK-NEXT:    [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
; CHECK-NEXT:    [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; CHECK-NEXT:    [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], +inf
; CHECK-NEXT:    [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; CHECK-NEXT:    [[TMP8:%.*]] = select i1 [[TMP6]], float 0.000000e+00, float [[TMP4]]
; CHECK-NEXT:    [[CALL:%.*]] = select i1 [[TMP7]], float +inf, float [[TMP8]]
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 -2)
  ret float %call
}

define double @test_pown_afn_f64(double %x, i32 %y) #0 {
; CHECK-LABEL: define double @test_pown_afn_f64(
; CHECK-SAME: double [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 [[Y]])
; CHECK-NEXT:    ret double [[CALL]]
;
entry:
  %call = tail call afn double @_Z4powndi(double %x, i32 %y)
  ret double %call
}

declare double @_Z4powndi(double, i32) #0

define <2 x double> @test_pown_afn_v2f64(<2 x double> %x, <2 x i32> %y) #0 {
; CHECK-LABEL: define <2 x double> @test_pown_afn_v2f64(
; CHECK-SAME: <2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x double> [[CALL]]
;
entry:
  %call = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)
  ret <2 x double> %call
}

declare <2 x double> @_Z4pownDv2_dDv2_i(<2 x double>, <2 x i32>) #0

define half @test_pown_afn_f16(half %x, i32 %y) #0 {
; CHECK-LABEL: define half @test_pown_afn_f16(
; CHECK-SAME: half [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 [[Y]])
; CHECK-NEXT:    ret half [[CALL]]
;
entry:
  %call = tail call afn half @_Z4pownDhi(half %x, i32 %y)
  ret half %call
}

declare half @_Z4pownDhi(half, i32) #0

define <2 x half> @test_pown_afn_v2f16(<2 x half> %x, <2 x i32> %y) #0 {
; CHECK-LABEL: define <2 x half> @test_pown_afn_v2f16(
; CHECK-SAME: <2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x half> [[CALL]]
;
entry:
  %call = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)
  ret <2 x half> %call
}

declare <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half>, <2 x i32>) #0

attributes #0 = { mustprogress nofree norecurse nounwind willreturn memory(none) }
attributes #1 = { mustprogress nofree nounwind willreturn memory(none) }