(amdgpu-usage-guide)=
:hidden: true AMDGPUModifierSyntax AMDGPUOperandSyntax AMDGPUInstructionSyntax AMDGPUInstructionNotation AMDGPUDwarfExtensionsForHeterogeneousDebugging AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack AMDGPU/DeveloperGuideline
The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the R600 family up until the current GCN families. It lives in the llvm/lib/Target/AMDGPU directory.
(amdgpu-target-triples)=
Use the Clang option --target=<Architecture><SubArch>-<Vendor>-<OS>-<Environment> to specify the target triple.
:::{note} Historically, the single top-level amdgcn architecture was used for all devices and specific devices by the subtarget. It has been replaced with the amdgpu architecture combined with a subarch suffix. The legacy spelling is accepted for accepted for compatibility. :::
:::{list-table} AMDGPU Architectures :name: amdgpu-architecture-table :header-rows: 1
r600amdgpuamdgcnamdgpu. :::The following table lists each major subarch and the minor subarches it covers. The Default Processor column gives the generic processor that a major subarch selects by default for code generation; this is the corresponding generic processor for families that have one (see {ref}amdgpu-generic-processor-table). Major subarches listed as (none) are placeholders for families that do not yet have a generic target. See {ref}amdgpu-subarch-compatibility for how subarches are matched.
:::{list-table} AMDGPU Subarchitectures :name: amdgpu-major-subarch-table :header-rows: 1
amdgpu6amdgpu6.00 (gfx600), amdgpu6.01 (gfx601), amdgpu6.02 (gfx602)amdgpu7amdgpu7.00 (gfx700), amdgpu7.01 (gfx701), amdgpu7.02 (gfx702), amdgpu7.03 (gfx703), amdgpu7.04 (gfx704), amdgpu7.05 (gfx705)amdgpu8amdgpu8.01 (gfx801), amdgpu8.02 (gfx802), amdgpu8.03 (gfx803), amdgpu8.05 (gfx805)amdgpu8.10amdgpu8.10 (gfx810)amdgpu9gfx9-genericamdgpu9.00 (gfx900), amdgpu9.02 (gfx902), amdgpu9.04 (gfx904), amdgpu9.06 (gfx906), amdgpu9.09 (gfx909), amdgpu9.0c (gfx90c)amdgpu9.08amdgpu9.08 (gfx908)amdgpu9.0aamdgpu9.0a (gfx90a)amdgpu9.4gfx9-4-genericamdgpu9.42 (gfx942), amdgpu9.50 (gfx950)amdgpu10.1gfx10-1-genericamdgpu10.10 (gfx1010), amdgpu10.11 (gfx1011), amdgpu10.12 (gfx1012), amdgpu10.13 (gfx1013)amdgpu10.3gfx10-3-genericamdgpu10.30 (gfx1030), amdgpu10.31 (gfx1031), amdgpu10.32 (gfx1032), amdgpu10.33 (gfx1033), amdgpu10.34 (gfx1034), amdgpu10.35 (gfx1035), amdgpu10.36 (gfx1036)amdgpu11gfx11-genericamdgpu11.00 (gfx1100), amdgpu11.01 (gfx1101), amdgpu11.02 (gfx1102), amdgpu11.03 (gfx1103), amdgpu11.50 (gfx1150), amdgpu11.51 (gfx1151), amdgpu11.52 (gfx1152), amdgpu11.53 (gfx1153) amdgpu11.54 (gfx1154)amdgpu11.7gfx11-7-genericamdgpu11.70 (gfx1170), amdgpu11.71 (gfx1171), amdgpu11.72 (gfx1172)amdgpu12gfx12-genericamdgpu12.00 (gfx1200), amdgpu12.01 (gfx1201)amdgpu12.5sgfx1250-strictamdgpu12.50s (gfx1250-strict)amdgpu12.5gfx12-5-genericamdgpu12.50 (gfx1250), amdgpu12.51 (gfx1251)amdgpu13gfx13-genericamdgpu13.10 (gfx1310) ::::::{list-table} AMDGPU Vendors :name: amdgpu-vendor-table :header-rows: 1
amdmesamesa3d. ::::::{list-table} AMDGPU Operating Systems :name: amdgpu-os :header-rows: 1
amdhsa
Compute kernels executed on HSA [{ref}HSA <hsa>] compatible runtimes such as:
AMD-ROCm <amd-rocm>] using the rocm-amdhsa loader on Linux. See AMD ROCm Platform Release Notes [{ref}AMD-ROCm-Release-Notes <amd-rocm-release-notes>] for supported hardware and software.amdpalmesa3d:::{list-table} AMDGPU Environments :name: amdgpu-environment-table :header-rows: 1
(amdgpu-subarch-compatibility)=
For the amdgpu architecture the ISA version is encoded in the triple's SubArch component. Every unique ISA has its own minor subarch (for example amdgpu9.00 for gfx900). amdgcn is a legacy alias of amdgpu (see {ref}amdgpu-architecture-table) which does not support subarches.
Minor subarches are grouped into major subarches that name a family of largely compatible ISA versions (for example amdgpu9). A major subarch corresponds to a {ref}generic processor <amdgpu-generic-processor-table> when one exists for that family; the remaining major subarches are placeholders for families that do not yet have a generic target for code generation.
Two subarches are considered compatible when:
In particular, two distinct minor subarches are never compatible with each other, even within the same family (for example amdgpu9.00 and amdgpu9.06 are not compatible). A minor subarch is compatible with itself and its own major subarch, and a major subarch is compatible with itself and every minor subarch it covers. A triple with no subarch (amdgpu) is treated as compatible with anything, as a backwards-compatibility allowance. When linking modules with compatible-but-unequal subarches, the more specific (minor) subarch is selected for the merged module.
(amdgpu-processors)=
Use the Clang options -mcpu=<target-id> or --offload-arch=<target-id> to specify the AMDGPU processor together with optional target features. See {ref}amdgpu-target-id and {ref}amdgpu-target-features for AMD GPU target specific information.
Every processor supports every OS ABI (see {ref}amdgpu-os) with the following exceptions:
amdhsa is not supported in r600 architecture (see {ref}amdgpu-architecture-table).
:::{list-table} AMDGPU Processors :name: amdgpu-processor-table :header-rows: 1 :widths: auto
amdgpu-os <amdgpu-os> and corresponding runtime release notes for current information and level of support)AMD-RADEON-HD-2000-3000 <amd-radeon-hd-2000-3000>]r600r600r630r600rs880r600rv670r600AMD-RADEON-HD-4000 <amd-radeon-hd-4000>]rv710r600rv730r600rv770r600AMD-RADEON-HD-5000 <amd-radeon-hd-5000>]cedarr600cypressr600juniperr600redwoodr600sumor600AMD-RADEON-HD-6000 <amd-radeon-hd-6000>]bartsr600caicosr600caymanr600turksr600AMD-GCN-GFX6 <amd-gcn-gfx6>]gfx600tahitiamdgpu6.00gfx601pitcairnverdeamdgpu6.01gfx602hainanolandamdgpu6.02AMD-GCN-GFX7 <amd-gcn-gfx7>]gfx700kaveriamdgpu7.00gfx701hawaiiamdgpu7.01gfx702amdgpu7.02gfx703kabinimullinsamdgpu7.03gfx704bonaireamdgpu7.04gfx705
amdgpu7.05
APU
TBA
Add product names.
AMD-GCN-GFX8 <amd-gcn-gfx8>]gfx801carrizoamdgpu8.01gfx802icelandtongaamdgpu8.02gfx803fijiamdgpu8.03polaris10amdgpu8.03polaris11amdgpu8.03gfx805tongaproamdgpu8.05gfx810
stoneyamdgpu8.10
APU
TBA
Add product names.
AMD-GCN-GFX900-GFX904-VEGA <amd-gcn-gfx900-gfx904-vega>] [{ref}AMD-GCN-GFX906-VEGA7NM <amd-gcn-gfx906-vega7nm>] [{ref}AMD-GCN-GFX908-CDNA1 <amd-gcn-gfx908-cdna1>] [{ref}AMD-GCN-GFX90A-CDNA2 <amd-gcn-gfx90a-cdna2>] [{ref}AMD-GCN-GFX942-CDNA3 <amd-gcn-gfx942-cdna3>]gfx900amdgpu9.00gfx902amdgpu9.02gfx904
amdgpu9.05
dGPU
TBA
Add product names.
gfx906amdgpu9.06gfx908amdgpu9.08gfx909
amdgpu9.09
APU
TBA
Add product names.
gfx90aamdgpu9.0agfx90camdgpu9.0cgfx942amdgpu9.42gfx950
amdgpu9.50
dGPU
TBA
Add product names.
AMD-GCN-GFX10-RDNA1 <amd-gcn-gfx10-rdna1>]gfx1010amdgpu10.10gfx1011amdgpu10.11gfx1012amdgpu10.12gfx1013
amdgpu10.13
APU
TBA
Add product names.
AMD-GCN-GFX10-RDNA2 <amd-gcn-gfx10-rdna2>]gfx1030amdgpu10.30gfx1031amdgpu10.31gfx1032
amdgpu10.32
dGPU
TBA
Add product names.
gfx1033
amdgpu10.33
APU
TBA
Add product names.
gfx1034
amdgpu10.34
dGPU
TBA
Add product names.
gfx1035
amdgpu10.35
APU
TBA
Add product names.
gfx1036
amdgpu10.36
APU
TBA
Add product names.
AMD-GCN-GFX11-RDNA3 <amd-gcn-gfx11-rdna3>]gfx1100amdgpu11.00gfx1101amdgpu11.01gfx1102amdgpu11.02gfx1103
amdgpu11.03
APU
TBA
Add product names.
AMD-GCN-GFX11-RDNA3.5 <amd-gcn-gfx11-rdna3-5>]gfx1150
amdgpu11.50
APU
Radeon 890M
Add product names.
gfx1151
amdgpu11.51
APU
Radeon 8060S
Add product names.
gfx1152
amdgpu11.52
APU
Radeon 860M
Add product names.
gfx1153
amdgpu11.53
APU
TBA
Add product names.
gfx1154
amdgpu11.54
APU
TBA
Add product names.
gfx1170
amdgpu11.70
APU
TBA
Add product names.
gfx1171
amdgpu11.71
APU
TBA
Add product names.
gfx1172
amdgpu11.72
APU
TBA
Add product names.
AMD-GCN-GFX12-RDNA4 <amd-gcn-gfx12-rdna4>]gfx1200amdgpu12.00gfx1201amdgpu12.01gfx1250-strict
amdgpu12.50s
dGPU
TBA
Add product names.
gfx1250
amdgpu12.50
APU
TBA
Add product names.
gfx1251
amdgpu12.51
APU
TBA
Add product names.
gfx1310
amdgpu13.10
dGPU
TBA
Add product names.
:::
Generic processors allow execution of a single code object on any of the processors that it supports. Such code objects may not perform as well as those for the non-generic processors.
Generic processors are only available on code object V6 and above (see {ref}amdgpu-elf-code-object).
Generic processor code objects are versioned. See {ref}amdgpu-generic-processor-versioning for more information on how versioning works.
:::{list-table} AMDGPU Generic Processors :name: amdgpu-generic-processor-table :header-rows: 1 :widths: auto
gfx9-genericamdgpu9gfx900gfx902gfx904gfx906gfx909gfx90cv_mad_mix instructions are not available on gfx900, gfx902, gfx909, gfx90c
v_fma_mix instructions are not available on gfx904
sramecc is not available on gfx906
The following instructions are not available on gfx906:
v_fmac_f32v_xnor_b32v_dot4_i32_i8v_dot8_i32_i4v_dot2_i32_i16v_dot2_u32_u16v_dot4_u32_u8v_dot8_u32_u4v_dot2_f32_f16gfx9-4-genericamdgpu9.4gfx942gfx950gfx10-1-genericamdgpu10.1gfx1010gfx1011gfx1012gfx1013The following instructions are not available on gfx1011 and gfx1012
v_dot4_i32_i8v_dot8_i32_i4v_dot2_i32_i16v_dot2_u32_u16v_dot2c_f32_f16v_dot4c_i32_i8v_dot4_u32_u8v_dot8_u32_u4v_dot2_f32_f16BVH Ray Tracing instructions are not available on gfx1013
gfx10-3-genericamdgpu10.3gfx1030gfx1031gfx1032gfx1033gfx1034gfx1035gfx1036gfx11-generic
amdgpu11
gfx1100gfx1101gfx1102gfx1103gfx1150gfx1151gfx1152gfx1153gfx1154Various codegen pessimizations are applied to work around some hazards specific to some targets within this family.
Not all VGPRs can be used on:
gfx1100gfx1101gfx1151SALU floating point instructions are not available on:
gfx1100gfx1101gfx1102gfx1103SGPRs are not supported for src1 in dpp instructions for:
gfx1100gfx1101gfx1102gfx1103gfx11-7-genericamdgpu11.7gfx1170gfx1171gfx1172gfx12-genericamdgpu12gfx1200gfx1201gfx12-5-genericamdgpu12.5gfx1250gfx1251gfx13-genericamdgpu13gfx1310(amdgpu-generic-processor-versioning)=
Generic processor (see {ref}amdgpu-generic-processor-table) code objects are versioned (see {ref}amdgpu-elf-header-e_flags-table-v6-onwards) between 1 and 255. The version of non-generic code objects is always set to 0.
For a generic code object, adding a new supported processor may require the code generated for the generic target to be changed so it can continue to execute on the previously supported processors as well as on the new one. When this happens, the generic code object version number is incremented at the same time as the generic target is updated.
Each supported processor of a generic target is mapped to the version it was introduced in. A generic code object can execute on a supported processor if the version of the code object being loaded is greater than or equal to the version in which the processor was added to the generic target.
(amdgpu-target-features)=
Target features control how code is generated to support certain processor specific features. Not all target features are supported by all processors. The runtime must ensure that the features supported by the device used to execute the code match the features enabled when generating the code. A mismatch of features may result in incorrect execution, or a reduction in performance.
The target features supported by each processor are listed in {ref}amdgpu-processors.
Target features are controlled by exactly one of the following Clang options:
-mcpu=<target-id> or --offload-arch=<target-id>
The
-mcpuand--offload-archcan specify the target feature as optional components of the target ID. If omitted, the target feature has theanyvalue. See {ref}amdgpu-target-id.
-m[no-]<target-feature>
Target features not specified by the target ID are specified using a separate option. These target features can have an
onoroffvalue.onis specified by omitting theno-prefix, andoffis specified by including theno-prefix. The default if not specified isoff.
For example:
-mcpu=gfx908:xnack+
: Enable the xnack feature.
-mcpu=gfx908:xnack-
: Disable the xnack feature.
-mcumode
: Enable the cumode feature.
-mno-cumode
: Disable the cumode feature.
:::{list-table} AMDGPU Target Features :name: amdgpu-target-features-table :header-rows: 2
-m[no-]cumodeamdgpu-amdhsa-memory-model).sramecc
-mcpu--offload-archIf specified, generate code that can only be loaded and executed in a process that has a matching setting for SRAMECC.
If not specified for code object V2 to V3, generate code that can be loaded and executed in a process with SRAMECC enabled.
If not specified for code object V4 or above, generate code that can be loaded and executed in a process with either setting of SRAMECC.
-m[no-]tgsplit-m[no-]wavefrontsize64xnack
-mcpu--offload-archIf specified, generate code that can only be loaded and executed in a process that has a matching setting for XNACK replay.
If not specified for code object V2 to V3, generate code that can be loaded and executed in a process with XNACK replay enabled.
If not specified for code object V4 or above, generate code that can be loaded and executed in a process with either setting of XNACK replay.
XNACK replay can be used for demand paging and page migration. If enabled in the device, then if a page fault occurs the code may execute incorrectly unless generated with XNACK replay enabled, or generated for code object V4 or above without specifying XNACK replay. Executing code that was generated with XNACK replay enabled, or generated for code object V4 or above without specifying XNACK replay, on a device that does not have XNACK replay enabled will execute correctly but may be less performant than code generated for XNACK replay disabled. :::
(amdgpu-module-flags)=
AMDGPU-specific behaviour can be controlled via LLVM module flags (see {ref}Module Flags Metadata <module-flags-metadata> in the language reference). These flags are set by frontends and are consumed by the AMDGPU backend during code generation.
:::{list-table} AMDGPU Module Flags :name: amdgpu-module-flags-table :header-rows: 1
amdgpu.buffer.oob.mode
i32
Max
Controls out-of-bounds semantics for untyped buffer instructions (buffer_load / buffer_store).
0 (or absent): any. The module does not care about OOB semantics. This is an alias of strict that is allowed to link with any other module. Code generation is identical to strict.1: relaxed. The backend may merge misaligned buffer accesses for performance, even if that changes OOB behaviour, and will not split vector accesses that may produce unexpected OOB accesses.2: strict. The backend preserves per-byte OOB guarantees by preventing merging of misaligned buffer accesses that could straddle an OOB boundary (e.g. as required by Vulkan robustBufferAccess2) and by splitting vector accesses to buffer fat pointers that may produce incorrect results under a robust buffer access scheme. See {ref}amdgpu-fat-buffer-oob-handling for details.amdgpu.tbuffer.oob.modei32tbuffer_load / tbuffer_store).amdgpu.xnack
i32
Error
Controls XNACK (page fault) replay mode. This is ignored on targets which do not support xnack.
0: off. The module can only be loaded and executed in a process with XNACK replay disabled. Code generation is optimized for XNACK disabled.1: on. The module can only be loaded and executed in a process with XNACK replay enabled. Code generation assumes XNACK is enabled.At link time, modules with conflicting settings (0 vs 1) produce an error. Modules with any (absent flag) are compatible with any setting.
XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support XNACK. The current default kernel driver setting is XNACK disabled on the graphics ring and XNACK enabled on the compute ring. If XNACK is enabled, the VMEM latency can be worse. If XNACK is disabled, the 2 SGPRs otherwise reserved for the XNACK mask can be used for general purposes.
amdgpu.sramecc
i32
Error
Controls SRAMECC mode. This is ignored on targets which do not support SRAMECC on/off modes. Targets that support SRAMECC without on/off modes always have SRAMECC enabled.
0: off. The module can only be loaded and executed in a process with SRAMECC disabled.1: on. The module can only be loaded and executed in a process with SRAMECC enabled. Some instructions behave differently (e.g., D16 memory instructions).At link time, modules with conflicting settings (0 vs 1) produce an error. Modules with any (absent flag) are compatible with any setting. :::
:::{note} Frontends that require misaligned-access merging for performance should set both buffer OOB flags to 1 (relaxed). Frontends that require strict per-byte OOB guarantees should set the flags to 2 (strict) as needed. Modules that do not use buffer operations or are indifferent to OOB semantics (e.g. device libraries) should leave the flags absent. :::
(amdgpu-target-id)=
AMDGPU supports target IDs. See Clang Offload Bundler for a general description. The AMDGPU target specific information is:
processor
: Is an AMDGPU processor or alternative processor name specified in {ref}amdgpu-processor-table. The non-canonical form target ID allows both the primary processor and alternative processor names. The canonical form target ID only allows the primary processor name.
target-feature
: Is a target feature name specified in {ref}amdgpu-target-features-table that is supported by the processor. The target features supported by each processor is specified in {ref}amdgpu-processor-table. Those that can be specified in a target ID are marked as being controlled by -mcpu and --offload-arch. Each target feature must appear at most once in a target ID. The non-canonical form target ID allows the target features to be specified in any order. The canonical form target ID requires the target features to be specified in alphabetical order.
(amdgpu-target-id-v2-v3)=
The target ID syntax for code object V2 to V3 is the same as defined in Clang Offload Bundler except when used in the {ref}amdgpu-assembler-directive-amdgcn-target assembler directive and the bundle entry ID. In those cases it has the following BNF syntax:
<target-id> ::== <processor> ( "+" <target-feature> )*
Where a target feature is omitted if Off and present if On or Any.
:::{note} The code object V2 to V3 cannot represent Any and treats it the same as On. :::
(amdgpu-embedding-bundled-objects)=
AMDGPU supports the HIP and OpenMP languages that perform code object embedding as described in Clang Offload Bundler.
:::{note} The target ID syntax used for code object V2 to V3 for a bundle entry ID differs from that used elsewhere. See {ref}amdgpu-target-id-v2-v3. :::
(amdgpu-address-spaces)=
The AMDGPU architecture supports a number of memory address spaces. The address space names use the OpenCL standard names, with some additions.
The AMDGPU address spaces correspond to target architecture specific LLVM address space numbers used in LLVM IR.
The AMDGPU address spaces are described in {ref}amdgpu-address-spaces-table. Only 64-bit process address spaces are supported for the amdgcn target.
:::{list-table} AMDGPU Address Spaces :name: amdgpu-address-spaces-table :header-rows: 2 :widths: auto
:::
Generic
: The generic address space is supported unless the Target Properties column of {ref}amdgpu-processor-table specifies Does not support generic address space.
The generic address space uses the hardware flat address support for two fixed ranges of virtual addresses (the private and local apertures), that are outside the range of addressable global memory, to map from a flat address to a private or local address. This uses FLAT instructions that can take a flat address and access global, private (scratch), and group (LDS) memory depending on if the address is within one of the aperture ranges.
Flat access to scratch requires hardware aperture setup and setup in the kernel prologue (see {ref}amdgpu-amdhsa-kernel-prolog-flat-scratch). Flat access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup (see {ref}amdgpu-amdhsa-kernel-prolog-m0).
To convert between a private or group address space address (termed a segment address) and a flat address, the base address of the corresponding aperture can be used. For GFX7-GFX8 these are available in the {ref}amdgpu-amdhsa-hsa-aql-queue the address of which can be obtained with Queue Ptr SGPR (see {ref}amdgpu-amdhsa-initial-kernel-execution-state). For GFX9-GFX11 the aperture base addresses are directly available as inline constant registers SRC_SHARED_BASE/LIMIT and SRC_PRIVATE_BASE/LIMIT. In 64-bit address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32 which makes it easier to convert from flat to segment or segment to flat.
A global address space address has the same value when used as a flat address so no conversion is needed.
See also {ref}synthetic apertures<amdgpu-synthetic-apertures> which exist in the generic address space.
Global and Constant
: The global and constant address spaces both use global virtual addresses, which are the same virtual address space used by the CPU. However, some virtual addresses may only be accessible to the CPU, some only accessible by the GPU, and some by both.
Using the constant address space indicates that the data will not change during the execution of the kernel. This allows scalar read instructions to be used. As the constant address space could only be modified on the host side, a generic pointer loaded from the constant address space is safe to be assumed as a global pointer since only the device global memory is visible and managed on the host side. The vector and scalar L1 caches are invalidated of volatile data before each kernel dispatch execution to allow constant memory to change values between kernel dispatches.
Region
: The region address space uses the hardware Global Data Store (GDS). All wavefronts executing on the same device will access the same memory for any given region address. However, the same region address accessed by wavefronts executing on different devices will access different memory. It is higher performance than global memory. It is allocated by the runtime. The data store (DS) instructions can be used to access it.
Local
: The local address space uses the hardware Local Data Store (LDS) which is automatically allocated when the hardware creates the wavefronts of a work-group, and freed when all the wavefronts of a work-group have terminated. All wavefronts belonging to the same work-group will access the same memory for any given local address. However, the same local address accessed by wavefronts belonging to different work-groups will access different memory. It is higher performance than global memory. The data store (DS) instructions can be used to access it.
Private
: The private address space uses the hardware scratch memory support which automatically allocates memory when it creates a wavefront and frees it when a wavefronts terminates. The memory accessed by a lane of a wavefront for any given private address will be different to the memory accessed by another lane of the same or different wavefront for the same private address.
If a kernel dispatch uses scratch, then the hardware allocates memory from a pool of backing memory allocated by the runtime for each wavefront. The lanes of the wavefront access this using dword (4 byte) interleaving. The mapping used from private address to backing memory address is:
wavefront-scratch-base + ((private-address / 4) * wavefront-size * 4) + (wavefront-lane-id * 4) + (private-address % 4)
If each lane of a wavefront accesses the same private address, the interleaving results in adjacent dwords being accessed and hence requires fewer cache lines to be fetched.
There are different ways that the wavefront scratch base address is determined by a wavefront (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).
Scratch memory can be accessed in an interleaved manner using buffer instructions with the scratch buffer descriptor and per wavefront scratch offset, by the scratch instructions, or by flat instructions. Multi-dword access is not supported except by flat and scratch instructions in GFX9-GFX11.
On targets without “Globally Accessible Scratch” (introduced in GFX125x), code that manipulates the stack values in other lanes of a wavefront, such as by addrspacecast-ing stack pointers to generic ones and taking offsets that reach other lanes or by explicitly constructing the scratch buffer descriptor, triggers undefined behavior when it modifies the scratch values of other lanes. The compiler may assume that such modifications do not occur for such targets.
When using code object V5 LIBOMPTARGET_STACK_SIZE may be used to provide the private segment size in bytes, for cases where a dynamic stack is used.
Constant 32-bit
: TODO
Buffer Fat Pointer
: The buffer fat pointer is an experimental address space that is currently unsupported in the backend. It exposes a non-integral pointer that is in the future intended to support the modelling of 128-bit buffer descriptors plus a 32-bit offset into the buffer (in total encapsulating a 160-bit pointer), allowing normal LLVM load/store/atomic operations to be used to model the buffer descriptors used heavily in graphics workloads targeting the backend.
The buffer descriptor used to construct a buffer fat pointer must be raw: the stride must be 0, the “add tid” flag must be 0, the swizzle enable bits must be off, and the extent must be measured in bytes. (On subtargets where bounds checking may be disabled, buffer fat pointers may choose to enable it or not). The cache swizzle support introduced in gfx942 may be used.
These pointers can be created by addrspacecast from a buffer resource (ptr addrspace(8)) or by using llvm.amdgcn.make.buffer.rsrc to produce a ptr addrspace(7) directly, which produces a buffer fat pointer with an initial offset of 0 and prevents the address space cast from being rewritten away.
The align attribute on operations from buffer fat pointers is deemed to apply to all componenents of the pointer - that is, an align 4 load is expected to both have the offset be a multiple of 4 and to have a base pointer with an alignment of 4.
This componentwise definition of alignment is needed to allow for promotion of aligned loads to s_buffer_load, which requires that both the base pointer and offset be appropriately aligned.
Buffer Resource
: The buffer resource pointer, in address space 8, is the newer form for representing buffer descriptors in AMDGPU IR, replacing their previous representation as <4 x i32>. It is a non-integral pointer that represents a 128-bit buffer descriptor resource (V#).
Since, in general, a buffer resource supports complex addressing modes that cannot be easily represented in LLVM (such as implicit swizzled access to structured buffers), performing address computations such as getelementptr is not recommended on ptr addrspace(8)s (if such computations are performed, the offset must be wavefront-uniform.) Note that such a usage of GEP is currently unimplemented in the backend, as it would require a wrapping 48-bit addition. Buffer resources may be passed to AMDGPU buffer intrinsics, and they may be converted to and from i128.
Casting a buffer resource to a buffer fat pointer is permitted and adds an offset of 0.
Buffer resources can be created from 64-bit pointers (which should be either generic or global) using the llvm.amdgcn.make.buffer.rsrc intrinsic, which takes the pointer, which becomes the base of the resource, the 16-bit stride (and swizzle control) field stored in bits 63:48 of a V#, the NumRecords/extent field, and the 32-bit flags field. NumRecords may be any integer width and is zero-extended or truncated to the target resource field width. The specific interpretation of these fields varies by the target architecture and is detailed in the ISA descriptions.
On gfx1250, the base pointer is instead truncated to 57 bits and the NumRecords field is 45 bits.
When buffer resources are passed to buffer intrinsics such as llvm.amdgcn.raw.ptr.buffer.load or llvm.amdgcn.struct.ptr.buffer.store, the align attribute on the pointer is assumed to apply to both the offset and the base pointer value. That is, align 8 means that both the base address within the ptr addrspace(8) and the offset argument have their three lowest bits set to 0. If the stride of the resource is nonzero, the stride must be a multiple of the given alignment.
In other words, the align attribute specifies the alignment of the effective address being loaded from/stored to and acts as a guarantee that this is not achieved from adding lower-alignment parts (as hardware may not always allow for such an addition). For example, if a buffer resource has the base address 0xfffe and is accessed with a raw.ptr.buffer.load with an offset of 2, the load must not be marked align 4 (even though the effective adddress 0x10000 is so aligned) as this would permit the compiler to make incorrect transformations (such as promotion to s_buffer_load, which requires such componentwise alignment).
Buffer Strided Pointer
: The buffer index pointer is an experimental address space. It represents a 128-bit buffer descriptor and a 32-bit offset, like the Buffer Fat Pointer. Additionally, it contains an index into the buffer, which allows the direct addressing of structured elements. These components appear in that order, i.e., the descriptor comes first, then the 32-bit offset followed by the 32-bit index.
The bits in the buffer descriptor must meet the following requirements: the stride is the size of a structured element, the “add tid” flag must be 0, and the swizzle enable bits must be off.
These pointers can be created by addrspacecast from a buffer resource (ptr addrspace(8)) or by using llvm.amdgcn.make.buffer.rsrc to produce a ptr addrspace(9) directly, which produces a buffer strided pointer whose initial index and offset values are both 0. This prevents the address space cast from being rewritten away.
As with buffer fat pointers, alignment of a buffer strided pointer applies to both the base pointer address and the offset. In addition, the alignment also constrains the stride of the pointer. That is, if you do an align 4 load from a buffer strided pointer, this means that the base pointer is align(4), that the offset is a multiple of 4 bytes, and that the stride is a multiple of 4.
VGPR
: The VGPR address space presents a memory view of the wave‘s vector registers. The 32-bit address is a byte address into the thread’s view of vector registers. For example, loading 4 bytes from address 12 reads the contents of v3. Storing 8 bytes to address 32 overwrites the contents of v[8:9].
Use of this address space by frontends is strongly discouraged. It has unusual and subtle lifetime rules due to the potential for interaction with normal register allocation. It exists primarily for internal purposes of the backend, such as promoting alloca instructions from the private address space into VGPRs.
In particular, memory in this address space that was allocated by an alloca is not visible while in a called function. Attempting to dereference a pointer to such memory in a called function is undefined behavior.
Barrier
: This address space represents barrier IDs (introduced in GFX12) as addresses. It does not map directly to any addressable memory and is implemented using {ref}synthetic apertures<amdgpu-synthetic-apertures>, thus pointers into this address space:
Pointer are 32 bits and directly correspond to valid barrier IDs. When consumed by an intrinsic, all barrier pointers must, when interpreted as signed 32 bit integers, have a value corresponding to a valid barrier ID on the target. Otherwise, the behavior is undefined.
The NULL pointer (as a constant) can be consumed by some intrinsics and corresponds to the NULL named barrier.
Streamout Registers
: Dedicated registers used by the GS NGG Streamout Instructions. The register file is modelled as a memory in a distinct address space because it is indexed by an address-like offset in place of named registers, and because register accesses affect LGKMcnt. This is an internal address space used only by the compiler. Do not use this address space for IR pointers.
(amdgpu-synthetic-apertures)=
Synthetic apertures are defined that enable safe roundtrips of pointers from special address spaces through the generic address space. Attempting to dereference generic pointers obtained in this way (using e.g. load or store) has undefined behavior.
The address size of an address spaces that use synthetic apertures can only be 32 bits wide or less. The full width of the source pointer is usable and preserved when converting it from/to the generic address space.
The following synthetic apertures are defined:
:::{list-table} AMDGPU Synthetic Apertures :name: amdgpu-synthetic-apertures-table :widths: 30 10 30 30 :header-rows: 1
Address Space <amdgpu-address-spaces-table>0x00000001Converting a pointer to generic (64 bits) using synthetic apertures is done as follows:
The value of the source pointer (32 bits) becomes the lower 32 bits of the generic pointer.
The upper 32 bits are a bitwise OR of:
The upper 32 bits of the LDS segment aperture.
The relevant mask in the {ref}above table<amdgpu-synthetic-apertures-table>.
The conversion back to the original address space can simply be done by discarding the upper 32 bits of the generic pointer.
As the LDS aperture is defined by its 16 most significant bits, we can theoretically support up to (1 << 16) - 1 synthetic apertures safely.
(amdgpu-memory-scopes)=
:::{note} {ref}amdgpu-memmodel is a work in progress to provide a complete memory consistency model for AMDGPU, including newer features like availability, visibility and asynchronous operations. The new model will replace the model described in this section. Until then, this section should only be read along with the new model; any ambiguity is likely to be settled in favour of the new model. :::
This section provides LLVM memory synchronization scopes supported by the AMDGPU backend memory model when the target triple OS is amdhsa (see {ref}amdgpu-amdhsa-memory-model and {ref}amdgpu-target-triples).
The memory model supported is based on the HSA memory model [{ref}HSA <hsa>] which is based in turn on HRF-indirect with scope inclusion [{ref}HRF <hrf>]. The happens-before relation is transitive over the synchronizes-with relation independent of scope and synchronizes-with allows the memory scope instances to be inclusive (see table {ref}amdgpu-amdhsa-llvm-sync-scopes-table). Concurrent atomic operations only operate atomically with respect to each other if they are included in each other's sync scope. If a read R and the writes it may see are atomic but do not all have inclusive scopes, then R returns undef (see {ref}memmodel).
This is different to the OpenCL [{ref}OpenCL <opencl>] memory model which does not have scope inclusion and requires the memory scopes to exactly match. However, this is conservatively correct for OpenCL.
There is a one-as variant for each sync scope. If a release or acquire operation with a one-as sync scope participates in a synchronization, only the effects of memory operations in the address space of the one-as operation are synchronized. The address space of a fence instruction with one-as sync scope is specified via amdgpu-synchronize-as MMRAs (see {ref}amdgpu-fence-as).
:::{note} The behavior of one-as sync scopes is currently not well-founded in the memory model. Synchronization via a one-as sync scope effectively causes the happens-before relation to be non-transitive. :::
:::{list-table} AMDHSA LLVM Sync Scopes :name: amdgpu-amdhsa-llvm-sync-scopes-table :header-rows: 1 :widths: auto
none
The default: system.
Synchronizes with, and participates in modification and seq_cst total orderings with, other operations (except image operations) for all address spaces (except private, or generic that accesses private) provided the other operation's sync scope is:
system.agent and executed by a thread on the same agent.workgroup and executed by a thread in the same work-group.wavefront and executed by a thread in the same wavefront.agent
Synchronizes with, and participates in modification and seq_cst total orderings with, other operations (except image operations) for all address spaces (except private, or generic that accesses private) provided the other operation's sync scope is:
system or agent and executed by a thread on the same agent.workgroup and executed by a thread in the same work-group.wavefront and executed by a thread in the same wavefront.cluster
Synchronizes with, and participates in modification and seq_cst total orderings with, other operations (except image operations) for all address spaces (except private, or generic that accesses private) provided the other operation's sync scope is:
system, agent or cluster and executed by a thread on the same cluster.workgroup and executed by a thread in the same work-group.wavefront and executed by a thread in the same wavefront.On targets that do not support workgroup cluster launch mode, this behaves like agent scope instead.
workgroup
Synchronizes with, and participates in modification and seq_cst total orderings with, other operations (except image operations) for all address spaces (except private, or generic that accesses private) provided the other operation's sync scope is:
system, agent or workgroup and executed by a thread in the same work-group.wavefront and executed by a thread in the same wavefront.wavefront
Synchronizes with, and participates in modification and seq_cst total orderings with, other operations (except image operations) for all address spaces (except private, or generic that accesses private) provided the other operation's sync scope is:
system, agent, workgroup or wavefront and executed by a thread in the same wavefront.singlethreadone-assystem but only synchronizes with other operations within the same address space.agent-one-asagent but only synchronizes with other operations within the same address space.cluster-one-ascluster but only synchronizes with other operations within the same address space.workgroup-one-asworkgroup but only synchronizes with other operations within the same address space.wavefront-one-aswavefront but only synchronizes with other operations within the same address space.singlethread-one-assinglethread but only synchronizes with other operations within the same address space. :::(amdgpu-fat-buffer-oob-handling)=
Instructions that load from or store to buffer resources (and thus, by extension buffer fat pointers and buffer strided pointers) generally implement handling for out of bounds (OOB) memory accesses, including those that are partially OOB, if the buffer resource resource has the required flags set. How ordinary load and store instructions are lowered to buffer operations is partly controlled by the amdgpu.buffer.oob.mode (see {ref}amdgpu-module-flags). If that flag is set to 1 (relaxed), no handling to improve the expected behavior of OOB accesses is performed, while if it is set to 0 (any) or 2 (strict), operations may be split to ensure correctness under stronger models of how out-of-bounds accesses should behave.
When operating on more than 32 bits of data, the voffset used for the access will be range-checked for each 32-bit word independently. This check uses saturating arithmetic and interprets the offset as an unsigned value.
The behavior described above conflicts with the ABI requirements of certain graphics APIs that require out of bounds accesses to be handled strictly so that accessed that begin out of bounds but then access in-bounds elements (such as loading a <4 x i32> beginning at offset -4) still load the three in-bounds integers (producing <0, v0, v1, v2> and not <0, 0, 0, 0>. So, under strict OOB handling, such an access will be split into four i32 accesses. Note this this can only happen for underaligned loads - such wraparound isn't possible for loads that are alligned to their natural size.
Similarly, buffer fat pointers permit operating on types such as <8 x i8> which must be accessed (and bounds-checked) 4 bytes at a time. Non-word-aligned accesses to such types from near the end of a buffer resource (such as starting a load of an <8 x i8> from an offset of 6 on an 8-byte buffer) will treat the initial two bytes to be loaded/stored as out of bounds, even though, under a strict interpretation of the bounds-checking semantics, they would be in bounds. Under strict OOB handling, such a load will be split into a sequence of <2 x i16> loads.
:::{note} No attempt will be made to shrink buffer intrinsic calls (calling llvm.amdgcn.raw.ptr.buffer.* directly) in order to cause them to meet the requirements of strict OOB mode. However, in strict OOB mode, those intrinsics will not be combined in a way that would violate the guarantees of that mode. :::
The AMDGPU backend implements some target extension types.
(amdgpu-types-named-barriers)=
Named barriers are fixed function hardware barrier objects that are available in gfx12.5+ in addition to the traditional default barriers.
In LLVM IR, named barriers are represented by global variables of type target("amdgcn.named.barrier", 0) in the barrier address space. Programs in LLVM IR refer to named barriers using pointers.
The following named barrier types are supported in global variables, defined recursively:
target("amdgcn.named.barrier", 0)@bar = addrspace(15) global target("amdgcn.named.barrier", 0) undef @foo = addrspace(15) global [2 x target("amdgcn.named.barrier", 0)] undef @baz = addrspace(15) global { target("amdgcn.named.barrier", 0) } undef ... %foo.i = getelementptr [2 x target("amdgcn.named.barrier", 0)], ptr addrspace(15) @foo, i32 0, i32 %i call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(15) %foo.i, i32 0)
Named barrier types may not be used in alloca.
Named barriers do not have an underlying byte representation. It is undefined behavior to use a pointer to any part of a named barrier object as the pointer operand of a regular memory access instruction or intrinsic. Pointers to named barrier objects are intended to be used with dedicated intrinsics. Reading from or writing to such pointers is undefined behavior.
stridemark)The strided buffer marker type target("amdgpu.stridemark") is a type used to allow representing the mixed index/offset access provided by buffer instructions, which is used with ptr addrspace(9) - a pointer that carries both indices.
This type is a compile-time marker that has no real value and appears only in element type metadata. No value of this type can be created.
The marker type has one optional parameter - an integer indicating the constant value of the stride of the buffer(s) being addressed if known. That integer, if given, must be non-negative (but can be 0, indicating the degenarate case where no stride is set but the index field should be used anyway).
When creating a structured GEP, arrays of amdgpu.stridemarks are used to represent indexing into the index component of the structured/strided buffer, while a subsequent bare getelementptr - is used to manipulate the offset part.
Example usage:
;; A 2-D array of unknown length and stride. %q1 = call ptr addrspace(9) (ptr addrspace(9), ...) (ptr addrspace(9) elementtype([0 x target("amdgpu.stridemark") ]) %p, i32 %index) %q = getelementptr i8, ptr addrspace(9) %q1, i32 %offset ;; Known bounds on index and offset. %y1 = call ptr addrspace(9) (ptr addrspace(9), ...) (ptr addrspace(9) elementtype([256 x target("amdgpu.stridemark", 16) ]) %p, i32 %index) %y = getelementptr ptr addrspace(9) %y1, i32 %offset
Note that the lowering for these examples is not yet implemented and will be added in future changes.
The AMDGPU backend implements the following LLVM IR intrinsics.
This section is WIP.
:::{list-table} AMDGPU LLVM IR Intrinsics :name: amdgpu-llvm-ir-intrinsics-table :header-rows: 1 :widths: auto
llvm.frexp <int_frexp>llvm.log2 <int_log2>llvm.sqrt <int_sqrt>llvm.log <int_log>llvm.exp <int_exp>llvm.log10 <int_log10>llvm.exp2 <int_exp2>llvm.stacksave.p5 <int_stacksave>llvm.stackrestore.p5 <int_stackrestore>llvm.get.fpmode.i32 <int_get_fpmode>{ref}llvm.get.rounding<int_get_rounding>
AMDGPU supports two separately controllable rounding modes depending on the floating-point type. One controls float, and the other controls both double and half operations. If both modes are the same, returns one of the standard return values. If the modes are different, returns one of {ref}12 extended values <amdgpu-rounding-mode-enumeration-values-table> describing the two modes.
To nearest, ties away from zero is not a supported mode. The raw rounding mode values in the MODE register do not exactly match the FLT_ROUNDS values, so a conversion is performed.
llvm.set.rounding<int_set_rounding>llvm.get.rounding’. Rounding mode is undefined if not passed a valid input. This should be a wave uniform value. In case of a divergent input value, the first active lane's value will be used.llvm.get.fpenv<int_get_fpenv>llvm.set.fpenv<int_set_fpenv>Iterative strategy, and 2: DPP. If the target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is implemented for i32 and i64 types.llvm.amdgcn.wave.reduce.umin, but performs a signed min reduction on signed integers. Intrinsic is implemented for i32 and i64 types.llvm.amdgcn.wave.reduce.umin, but performs a floating point min reduction on floating point values. Intrinsic is implemented for float and double types. Intrinsic is modelled similar to llvm.minnum intrinsic. For a reduction between two NAN values, a NAN is returned. For a reduction between a NAN and a number, the number is returned. -0.0 < +0.0 is true for this reduction. The ordering behaviour of SNANs is non-deterministic.Iterative strategy, and 2: DPP. If the target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is implemented for i32 and i64 types.llvm.amdgcn.wave.reduce.umax, but performs a signed max reduction on signed integers. Intrinsic is implemented for i32 and i64 types.llvm.amdgcn.wave.reduce.umax, but performs a floating point max reduction on floating point values. Intrinsic is implemented for float and double types. Intrinsic is modelled similar to llvm.maxnum intrinsic. For a reduction between two NAN values, a NAN is returned. For a reduction between a NAN and a number, the number is returned. -0.0 < +0.0 is true for this reduction. The ordering behaviour of SNANs is non-deterministic.Iterative strategy, and 2: DPP. If the target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is implemented for signed/unsigned i32 and i64 types.llvm.amdgcn.wave.reduce.add, but performs a floating point add reduction on floating point values. Intrinsic is implemented for float and double types.Iterative strategy, and 2: DPP. If the target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is implemented for signed/unsigned i32 and i64 types.llvm.amdgcn.wave.reduce.sub, but performs a floating point sub reduction on floating point values. Intrinsic is implemented for float and double types.Iterative strategy, and 2: DPP. If the target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is implemented for i32 and i64 types.llvm.amdgcn.wave.reduce.and, but performs a bitwise-or reduction on the values provided by each wavefront. Intrinsic is implemented for i32 and i64 types.llvm.amdgcn.wave.reduce.and, but performs a bitwise-xor reduction on the values provided by each wavefront. Intrinsic is implemented for i32 and i64 types.llvm.amdgcn.sched.barrier
Controls the types of instructions that may be allowed to cross the intrinsic during instruction scheduling. The parameter is a mask for the instruction types that can cross the intrinsic.
llvm.amdgcn.sched.group.barrier
Creates schedule groups with specific properties to create custom scheduling pipelines. The ordering between groups is enforced by the instruction scheduler. The intrinsic applies to the code that precedes the intrinsic. The intrinsic takes three values that control the behavior of the schedule groups.
The mask can include multiple instruction types. It is undefined behavior to set values beyond the range of valid masks.
Combining multiple sched_group_barrier intrinsics enables an ordering of specific instruction types during instruction scheduling. For example, the following enforces a sequence of 1 VMEM read, followed by 1 VALU instruction, followed by 5 MFMA instructions.
// 1 VMEM read__builtin_amdgcn_sched_group_barrier(32, 1, 0)// 1 VALU__builtin_amdgcn_sched_group_barrier(2, 1, 0)// 5 MFMA__builtin_amdgcn_sched_group_barrier(8, 5, 0)
llvm.amdgcn.iglp.opt
An experimental intrinsic for instruction group level parallelism. The intrinsic implements predefined instruction scheduling orderings. The intrinsic applies to the surrounding scheduling region. The intrinsic takes a value that specifies the strategy. The compiler implements two strategies.
Only one iglp_opt intrinsic may be used in a scheduling region. The iglp_opt intrinsic cannot be combined with sched_barrier or sched_group_barrier.
The iglp_opt strategy implementations are subject to change.
llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4
Emit v_mfma_scale_f32_16x16x128_f8f6f4 to set the scale factor. The last 4 operands correspond to the scale inputs.
v_mfma_scale_f32_32x32x64_f8f6f4v_permlane16_swap_b32 instruction on supported targets. Swaps the values across lanes of first 2 operands. Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes). Returns a pair for the swapped registers. The first element of the return corresponds to the swapped element of the first argument.v_permlane32_swap_b32 instruction on supported targets. Swaps the values across lanes of first 2 operands. Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes). Returns a pair for the swapped registers. The first element of the return corresponds to the swapped element of the first argument.llvm.amdgcn.update.dpp
The llvm.amdgcn.update.dpp.`<type>` intrinsic represents the update.dpp operation in AMDGPU. It takes an old value, a source operand, a DPP control operand, a row mask, a bank mask, and a bound control. Various data types are supported, including, bf16, f16, f32, f64, i16, i32, i64, p0, p3, p5, v2f16, v2f32, v2i16, v2i32, v2p0, v3i32, v4i32, v8f16. This operation is equivalent to a sequence of v_mov_b32 operations. It is preferred over llvm.amdgcn.mov.dpp.`<type>` for future use. llvm.amdgcn.update.dpp.<type> <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl> Should be equivalent to:
v_mov_b32 <dest> <old>v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>{ref}llvm.prefetch <int_prefetch>
Implemented on gfx1250, ignored on earlier targets. First argument is flat, global, or constant address space pointer. Any other address space is not supported. On gfx125x generates flat_prefetch_b8 or global_prefetch_b8 and brings data to GL2. Second argument is rw and currently ignored. Can be 0 or 1. Third argument is locality, 0-3. Translates to memory scope:
Note that SCOPE_CU is not generated and not safe on an invalid address. Fourth argument is cache type:
Instruction cache prefetches are unsafe on invalid address.
amdgpu-amdhsa-execution-barriers.amdgpu-amdhsa-execution-barriers. Available starting GFX12.5.i32 immediate argument. See {ref}amdgpu-amdhsa-execution-barriers. Available starting GFX12.i32 immediate expected count. The expected count of the barrier object is only set when the argument is not zero, and when the barrier object is a named barrier object. See {ref}amdgpu-amdhsa-execution-barriers. Available starting GFX12.i32 immediate argument. Returns i1 1 if the wave is running in a workgroup, and it was the first wave to arrive at the barrier object, otherwise returns i1 0. See {ref}amdgpu-amdhsa-execution-barriers. Available starting GFX12.i16 immediate argument. If waiting on a named barrier object, this instruction always waits on the last named barrier object that the thread has joined, even if it is different from the argument. See {ref}amdgpu-amdhsa-execution-barriers. Available starting GFX12.amdgpu-amdhsa-execution-barriers. Available starting GFX12.5.amdgpu-amdhsa-execution-barriers. Available starting GFX12.5.llvm.amdgcn.flat.load.monitor
Available on GFX12.5 only. Corresponds to flat_load_monitor_b32/64/128 (.b32/64/128 suffixes) instructions. For the purposes of the memory model, this is an atomic load operation in the generic (flat) address space.
This intrinsic has 3 operands:
Load Atomic Ordering<amdgpu-intrinsics-c-abi-atomic-memory-ordering-operand>.Synchronization Scope<amdgpu-intrinsics-syncscope-metadata-operand>.llvm.amdgcn.global.load.monitor
Available on GFX12.5 only. Corresponds to global_load_monitor_b32/64/128 (.b32/64/128 suffixes) instructions. For the purposes of the memory model, this is an atomic load operation in the global address space.
This intrinsic has 3 operands:
Load Atomic Ordering<amdgpu-intrinsics-c-abi-atomic-memory-ordering-operand>.Synchronization Scope<amdgpu-intrinsics-syncscope-metadata-operand>.llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64
Available starting GFX12.5. Corresponds to ds_atomic_barrier_arrive_rtn_b64.
For the purposes of the memory model, this is a monotonic atomic read-modify-write operation in the local address space.
This intrinsic has 2 operands:
Returns the LDS barrier data as it was before this operation was executed.
llvm.amdgcn.ds.atomic.async.barrier.arrive.b64
Available starting GFX12.5. Corresponds to ds_atomic_async_barrier_arrive_b64.
For the purposes of the memory model, this is an asynchronous monotonic atomic read-modify-write operation in the local address space.
This intrinsic has 1 operand:
:::{todo} List AMDGPU intrinsics. :::
(amdgpu-av-load-store)=
llvm.amdgcn.av’ IntrinsicsThe ‘llvm.amdgcn.av’ intrinsics perform {ref}store-available<amdgpu-store-available> and {ref}load-visible<amdgpu-load-visible> operations on flat or global memory with scope supplied as a metadata argument.
The pointer argument can be a global pointer (addrspace(1)) or a flat pointer (addrspace(0)). Global pointers select global_load/ global_store instructions; flat pointers select flat_load/ flat_store instructions. The cache policy bits are the same in both cases.
<4 x i32> @llvm.amdgcn.av.load.b128.p1( ptr addrspace(1), ; source (global) metadata) ; scope - e.g. '!0' where '!0 = !{!"workgroup"}' <4 x i32> @llvm.amdgcn.av.load.b128.p0( ptr, ; source (flat) metadata) ; scope void @llvm.amdgcn.av.store.b128.p1( ptr addrspace(1), ; destination (global) <4 x i32>, ; value metadata) ; scope void @llvm.amdgcn.av.store.b128.p0( ptr, ; destination (flat) <4 x i32>, ; value metadata) ; scope
This section is informational and for internal reference only. Users should not rely on the expansions described below. The only reliable user-level guarantees are those provided by the {ref}AMDGPU memory model<amdgpu-memmodel>.
The tables below show the cache policy bits for global pointer variants. Flat pointer variants use the corresponding flat_load/flat_store instructions with the same cache policy bits.
TODO: Currently the compiler does not support WGP mode on gfx12+. Hence, "workgroup" scope currently maps to CU scope (no bits). When WGP mode is enabled this should map to scope:SCOPE_SE.
:::{list-table} AMDGPU Load-Visible Implementation :class: longtable :header-rows: 1
global_load_dwordx4glcglcglcglobal_load_dwordx4sc0sc1sc1sc0 sc1global_load_dwordx4sc0sc1sc1sc0 sc1global_load_dwordx4glc dlcglc dlcglc dlcglobal_load_dwordx4glcglc dlcglc dlcglc dlcglobal_load_b128glcglcglcglobal_load_b128glcglcglcglcglobal_load_b128SCOPE_CUSCOPE_CUSCOPE_SESCOPE_DEVSCOPE_SYS ::::::{list-table} AMDGPU Store-Available Implementation :class: longtable :header-rows: 1
global_store_dwordx4global_store_dwordx4sc0sc1sc1sc0 sc1global_store_dwordx4sc0sc1sc1sc0 sc1global_store_dwordx4global_store_b128global_store_b128SCOPE_CUSCOPE_CUSCOPE_SESCOPE_DEVSCOPE_SYS :::Note: Cache control bits for Store are not affected by WGP mode.
llvm.amdgcn.cooperative.atomic’ IntrinsicsThe llvm.amdgcn.cooperative.atomic {ref}family of intrinsics<amdgpu-cooperative-atomic-intrinsics-table> provide atomic load and store operations to a naturally-aligned contiguous memory regions. Memory is accessed cooperatively by a collection of convergent threads, with each thread accessing a fraction of the contiguous memory region.
:::{todo} The memory model described here is imprecise; see SWDEV-536264. :::
This intrinsic has a memory ordering and may be used to synchronize-with another cooperative atomic. If the memory ordering is relaxed, it may pair with a fence if that same fence is executed by all participating threads with the same synchronization scope and set of address spaces.
In both cases, a synchronize-with relation can only be established between cooperative atomics with the same total access size.
Each target may have additional restrictions on how the intrinsic may be used; see {ref}the table below<amdgpu-llvm-ir-cooperative-atomic-intrinsics-availability>. Targets not covered in the table do not support these intrinsics.
:::{list-table} AMDGPU Cooperative Atomic Intrinsics Availability :name: amdgpu-llvm-ir-cooperative-atomic-intrinsics-availability :header-rows: 1 :widths: auto
amdgpu-amdhsa-memory-model-gfx125x-cooperative-atomics :::If the intrinsic is used without meeting all of the above conditions, or the target-specific conditions, then this intrinsic causes undefined behavior.
:::{list-table} AMDGPU Cooperative Atomic Intrinsics :name: amdgpu-cooperative-atomic-intrinsics-table :header-rows: 1 :widths: auto
llvm.amdgcn.cooperative.atomic.store.32x4Bllvm.amdgcn.cooperative.atomic.load.32x4Bllvm.amdgcn.cooperative.atomic.store.16x8Bllvm.amdgcn.cooperative.atomic.load.16x8Bllvm.amdgcn.cooperative.atomic.store.8x16Bllvm.amdgcn.cooperative.atomic.load.8x16BThe intrinsics are available for the global (.p1 suffix) and generic (.p0 suffix) address spaces.
The 3rd operand for .store or 2nd for .load intrinsics is the {ref}atomic ordering<amdgpu-intrinsics-c-abi-atomic-memory-ordering-operand> of the operation.
The last operand of the intrinsic is the {ref}synchronization scope<amdgpu-intrinsics-syncscope-metadata-operand> of the operation.
DMA intrinsics transfer data between global memory and LDS without occupying registers. See {ref}amdgpu-dma-operations for full documentation.
llvm.amdgcn.load[.async].to.lds
llvm.amdgcn.global.load[.async].lds
llvm.amdgcn.{raw|struct}[.ptr].buffer.load[.async].lds
llvm.amdgcn.{global|cluster}.load.async.to.lds.b{8,32,64,128}
llvm.amdgcn.global.store.async.from.lds.b{8,32,64,128}
Tensor intrinsics transfer data between global memory and LDS using a tensor descriptor. Despite the absence of .async in their names, these intrinsics are asynchronous. See {ref}amdgpu-dma-operations for full documentation.
llvm.amdgcn.tensor.{load.to|store.from}.lds
(amdgpu-intrinsics-c-abi-atomic-memory-ordering-operand)=
Intrinsic operands in this format are always i32 integer constants whose value is determined by the C ABI encoding of atomic memory orderings. The supported values are in {ref}the table below<amdgpu-intrinsics-c-abi-atomic-memory-orderings-table>.
:::{list-table} AMDGPU Intrinsics C ABI Atomic Memory Ordering Values :name: amdgpu-intrinsics-c-abi-atomic-memory-orderings-table :header-rows: 1 :widths: auto
i32 0relaxedi32 2acquirei32 3releasei32 5seq_cst:::
Example:
; "i32 5" is the atomic ordering operand %0 = tail call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr %addr, i32 5, metadata !0)
(amdgpu-intrinsics-syncscope-metadata-operand)=
Intrinsics operand in this format are metadata strings which must be one of the supported {ref}memory scopes<amdgpu-memory-scopes>. The metadata node must be made of a single MDString at the top level.
Example:
; "metadata !0" is the syncscope metadata operand.
%0 = tail call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr %addr, i32 4, metadata !0)
!0 = !{ !"agent" }
(amdgpu_unsupported_constructs)=
The following LLVM IR constructs are not supported by the AMDGPU backend:
This list is not exhaustive.
(amdgpu_metadata)=
The AMDGPU backend implements the following target custom LLVM IR metadata.
(amdgpu_last_use)=
amdgpu.last.use’ MetadataSets TH_LOAD_LU temporal hint on load instructions that support it. Takes priority over nontemporal hint (TH_LOAD_NT). This takes no arguments.
%val = load i32, ptr %in, align 4, !amdgpu.last.use !{}
amdgpu.no.remote.memory’ MetadataAsserts a memory operation does not access bytes in host memory, or remote connected peer device memory (the address must be device local). This is intended for use with {ref}atomicrmw <i_atomicrmw> and other atomic instructions. This is required to emit a native hardware instruction for some {ref}system scope <amdgpu-memory-scopes> atomic operations on some subtargets. For most integer atomic operations, this is a sufficient restriction to emit a native atomic instruction.
An {ref}atomicrmw <i_atomicrmw> without metadata will be treated conservatively as required to preserve the operation behavior in all cases. This will typically be used in conjunction with !amdgpu.no.fine.grained.memory.
; Indicates the atomic does not access fine-grained memory, or ; remote device memory. %old0 = atomicrmw sub ptr %ptr0, i32 1 acquire, !amdgpu.no.fine.grained.memory !0, !amdgpu.no.remote.memory !0 ; Indicates the atomic does not access peer device memory. %old2 = atomicrmw sub ptr %ptr2, i32 1 acquire, !amdgpu.no.remote.memory !0 !0 = !{}
(amdgpu_no_fine_grained_memory)=
amdgpu.no.fine.grained.memory’ MetadataAsserts a memory access does not access bytes allocated in fine-grained allocated memory. This is intended for use with {ref}atomicrmw <i_atomicrmw> and other atomic instructions. This is required to emit a native hardware instruction for some {ref}system scope <amdgpu-memory-scopes> atomic operations on some subtargets. An {ref}atomicrmw <i_atomicrmw> without metadata will be treated conservatively as required to preserve the operation behavior in all cases. This will typically be used in conjunction with !amdgpu.no.remote.memory.access.
; Indicates the access does not access fine-grained memory, or ; remote device memory. %old0 = atomicrmw sub ptr %ptr0, i32 1 acquire, !amdgpu.no.fine.grained.memory !0, !amdgpu.no.remote.memory.access !0 ; Indicates the access does not access fine-grained memory %old2 = atomicrmw sub ptr %ptr2, i32 1 acquire, !amdgpu.no.fine.grained.memory !0 !0 = !{}
(amdgpu_no_remote_memory_access)=
atomic.ignore.denormal.mode’ MetadataThis is generic IR metadata for floating-point {ref}atomicrmw <i_atomicrmw> operations; see {ref}'atomic.ignore.denormal.mode' Metadata <md_atomic.ignore.denormal.mode> in the language reference for its definition. It is required to emit a native atomic instruction for AMDGPU global memory, which unconditionally flushes float denormals.
On AMDGPU this is typically used in conjunction with !amdgpu.no.remote.memory.access and !amdgpu.no.fine.grained.memory.
This metadata was previously named amdgpu.ignore.denormal.mode.
%res0 = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst, align 4, !atomic.ignore.denormal.mode !0 %res1 = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst, align 4, !atomic.ignore.denormal.mode !0, !amdgpu.no.fine.grained.memory !0, !amdgpu.no.remote.memory.access !0 !0 = !{}
(amdgpu_expected_active_lanes)=
amdgpu.expected.active.lanes’ MetadataA profiling-derived hint describing how many lanes of the wavefront are expected to be active. The metadata has a single i32 constant operand giving the expected number of active lanes as an absolute count (the same value is used for both wave32 and wave64 targets). This structure is enforced by the verifier.
The AMDGPU atomic optimizer uses this metadata on LDS atomics to decide whether to skip the DPP optimization.
; Few expected active lanes: the atomic optimizer may skip the DPP optimization. %old0 = atomicrmw add ptr addrspace(3) @lds, i32 %val acq_rel, !amdgpu.expected.active.lanes !{i32 4} ; Many expected active lanes: the DPP optimization is not skipped. %old1 = atomicrmw add ptr addrspace(3) @lds, i32 %val acq_rel, !amdgpu.expected.active.lanes !{i32 32}
amdgpu.cfs’ MetadataSet the cache fill size (CFS) field in VMEM instructions for architectures that support it. Can be used on memory instructions (e.g. load) and memory intrinsics (e.g. llvm.amdgcn.image.load.1d).
The default value for the CFS field is 0 (256 bytes).
Valid arguments for CFS Metadata are:
The field indicates how much data is fetched on a cache miss. It is only supported on GFX13. GFX13 only honors it for load and atomic operations. GFX13 does not support a 32-byte fetch size so it treats CFS_32B the same as CFS_64B.
The AMDGPU backend supports the following LLVM IR attributes.
:::{list-table} AMDGPU LLVM IR Attributes :name: amdgpu-llvm-ir-attributes-table :header-rows: 1 :widths: auto
amdgpu_flat_work_group_size CLANG attribute [{ref}CLANG-ATTR <clang-attr>]. If the reqd_work_group_size metadata is present, the product of its three workgroup size dimensions must match both min and max. The IR implied default value is 1,1024. Clang may emit this attribute with more restrictive bounds depending on language defaults. If the actual block or workgroup size exceeds the limit at any point during the execution, the behavior is undefined. For example, even if there is only one active thread but the thread local id exceeds the limit, the behavior is undefined.opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table).amdgpu_num_sgpr CLANG attribute [{ref}CLANG-ATTR <clang-attr>]. Use "amdgpu-waves-per-eu" instead.amdgpu_num_vgpr CLANG attribute [{ref}CLANG-ATTR <clang-attr>]. Use "amdgpu-waves-per-eu" instead.amdgpu_waves_per_eu CLANG attribute [{ref}CLANG-ATTR <clang-attr>]. This is an optimization hint, and the backend may not be able to satisfy the request. If the specified range is incompatible with the function's “amdgpu-flat-work-group-size” value, the implied occupancy bounds by the workgroup size takes precedence.LDS DMA operations <amdgpu-dma-operations>.tgsplit-support feature.amdgpu_ps <amdgpu-cc>, and 0 for other calling conventions. Determines the necessity and type of null exports when a shader terminates early by killing lanes.spi_ps_input_addr register for {ref}amdgpu_ps <amdgpu-cc> shaders. Any bits enabled by this value will be enabled in the final register value.amdgpu-unroll-threshold, which controls the threshold used for full unrolling.amdgpu_max_num_work_groups CLANG attribute [{ref}CLANG-ATTR <clang-attr>]. Clang only emits this attribute when all the three numbers are >= 1.“amdgpu-agpr-alloc”=“min(,max)”
Indicates a minimum and maximum range for the number of AGPRs to make available to allocate. The values will be rounded up to the next multiple of the allocation granularity (4). The minimum value is interpreted as the minimum required number of AGPRs for the function to allocate (that is, the function requires no more than min registers). If only one value is specified, it is interpreted as the minimum register budget. The maximum will restrict allocation to use no more than max AGPRs.
The values may be ignored if satisfying it would violate other allocation constraints.
The behavior is undefined if a function which requires more AGPRs than the lower bound is reached through any function marked with a higher value of this attribute. A minimum value of 0 indicates the function does not require any AGPRs.
This is only relevant on targets with AGPRs which support accum_offset (gfx90a+).
“amdgpu-cluster-dims”=“x,y,z”
Specify the cluster workgroup dimensions. A value of “0,0,0” indicates that cluster is disabled. A value of “1024,1024,1024” indicates that cluster is enabled, but the dimensions cannot be determined at compile time. Any other value explicitly specifies the cluster dimensions.
This is only relevant on targets with cluster support.
“amdgpu-expert-scheduling-mode” true/false.
Enable expert scheduling mode 2 for this function. This is a hardware execution mode introduced in GFX12.
This is only relevant on GFX12+.
“amdgpu-no-fwd-progress”
Disable forward progress mode for wave priority (enabled by default).
Relevant for GFX10+. :::
The AMDGPU backend supports the following calling conventions:
:::{list-table} AMDGPU Calling Conventions :name: amdgpu-cc :header-rows: 1 :widths: auto
cccamdgpu-amdhsa-function-call-convention-non-kernel-functions for more details.fastccccc.coldccccc.amdgpu_csamdgpu_cs_chain
Similar to amdgpu_cs, with differences described below.
Functions with this calling convention cannot be called directly. They must instead be launched via the llvm.amdgcn.cs.chain intrinsic.
Arguments are passed in SGPRs, starting at s0, if they have the inreg attribute, and in VGPRs otherwise, starting at v8. Using more SGPRs or VGPRs than available in the subtarget is not allowed. On subtargets that use a scratch buffer descriptor (as opposed to scratch_{load,store}_* instructions), the scratch buffer descriptor is passed in s[48:51]. This limits the SGPR / inreg arguments to the equivalent of 48 dwords; using more than that is not allowed.
The return type must be void. Varargs, sret, byval, byref, inalloca, preallocated are not supported.
Values in scalar registers as well as v0-v7 are not preserved. Values in VGPRs starting at v8 are not preserved for the active lanes, but must be saved by the callee for inactive lanes when using WWM (a notable exception is when the llvm.amdgcn.init.whole.wave intrinsic is used in the function - in this case the backend assumes that there are no inactive lanes upon entry; any inactive lanes that need to be preserved must be explicitly present in the IR).
Chain functions receive a stack pointer from their caller (in s32), similar to amdgpu_gfx functions. If needed, the frame pointer is s33 and the base pointer is s34. Calls to amdgpu_gfx functions are allowed and behave like they do in amdgpu_cs functions.
A function may have multiple exits (e.g. one chain exit and one plain ret void for when the wave ends), but all llvm.amdgcn.cs.chain exits must be in uniform control flow.
amdgpu_cs_chain_preserveamdgpu_cs_chain, but active lanes for VGPRs starting at v8 are preserved. Calls to amdgpu_gfx functions are not allowed, and any calls to llvm.amdgcn.cs.chain must not pass more VGPR arguments than the caller's VGPR function parameters.amdgpu_esamdgpu_gfxamdgpu_gfx_whole_wave
Used for AMD graphics targets. Functions with this calling convention cannot be used as entry points. They must have an i1 as the first argument, which will be mapped to the value of EXEC on entry into the function. Other arguments will contain poison in their inactive lanes. Similarly, the return value for the inactive lanes is poison.
The function will run with all lanes enabled, i.e. EXEC will be set to -1 in the prologue and restored to its original value in the epilogue. The inactive lanes will be preserved for all the registers used by the function. Active lanes only will only be preserved for the callee saved registers.
In all other respects, functions with this calling convention behave like amdgpu_gfx functions.
amdgpu_gsamdgpu_hsamdgpu_kernelamdgpu-amdhsa-function-call-convention-kernel-functionsamdgpu_lsamdgpu_psamdgpu_vsThe following ABI conventions apply to all calling conventions that are used for callable functions (i.e. those that do not correspond to hardware entry points):
VMcnt, LOADcnt etc.) are in an indeterminate state.VScnt/STOREcnt.For entry points, the ABI conventions are dictated by the hardware behavior at wave launch and wave termination:
s_endpgm).As part of the AMDGPU MC layer, AMDGPU provides the following target-specific MCExprs.
:::{list-table} AMDGPU MCExpr types: :name: amdgpu-mcexpr-table :header-rows: 1 :widths: auto
max(arg, ...)min(arg, ...)or(arg, ...)A function‘s resource usage depends on each of its callees’ resource usage. The expressions used to denote resource usage reflect this by propagating each callees' equivalent expressions. Said expressions are emitted as symbols by the compiler when compiling to either assembly or object format and should not be overwritten or redefined.
The following describes all emitted function resource usage symbols:
:::{list-table} Function Resource Usage: :name: function-usage-table :header-rows: 1 :widths: auto
Furthermore, three symbols are additionally emitted describing the compilation unit's worst case (i.e, maxima) num_vgpr, num_agpr, and numbered_sgpr which may be referenced and used by the aforementioned symbolic expressions. These three symbols are amdgcn.max_num_vgpr, amdgcn.max_num_agpr, and amdgcn.max_num_sgpr.
(amdgpu-elf-code-object)=
The AMDGPU backend generates a standard ELF [{ref}ELF <elf>] relocatable code object that can be linked by lld to produce a standard ELF shared code object which can be loaded and executed on an AMDGPU target.
(amdgpu-elf-header)=
The AMDGPU backend uses the following ELF header:
:::{list-table} AMDGPU ELF Header :name: amdgpu-elf-header-table :header-rows: 1 :widths: auto
e_ident[EI_CLASS]ELFCLASS64e_ident[EI_DATA]ELFDATA2LSBe_ident[EI_OSABI]ELFOSABI_NONEELFOSABI_AMDGPU_HSAELFOSABI_AMDGPU_PALELFOSABI_AMDGPU_MESA3De_ident[EI_ABIVERSION]ELFABIVERSION_AMDGPU_HSA_V2ELFABIVERSION_AMDGPU_HSA_V3ELFABIVERSION_AMDGPU_HSA_V4ELFABIVERSION_AMDGPU_HSA_V5ELFABIVERSION_AMDGPU_HSA_V6ELFABIVERSION_AMDGPU_PALELFABIVERSION_AMDGPU_MESA3De_typeET_RELET_DYNe_machineEM_AMDGPUe_entrye_flagsamdgpu-elf-header-e_flags-v2-table, {ref}amdgpu-elf-header-e_flags-table-v3, {ref}amdgpu-elf-header-e_flags-table-v4-v5, and {ref}amdgpu-elf-header-e_flags-table-v6-onwards :::%
:::{list-table} AMDGPU ELF Header Enumeration Values :name: amdgpu-elf-header-enumeration-values-table :header-rows: 1 :widths: auto
EM_AMDGPUELFOSABI_NONEELFOSABI_AMDGPU_HSAELFOSABI_AMDGPU_PALELFOSABI_AMDGPU_MESA3DELFABIVERSION_AMDGPU_HSA_V2ELFABIVERSION_AMDGPU_HSA_V3ELFABIVERSION_AMDGPU_HSA_V4ELFABIVERSION_AMDGPU_HSA_V5ELFABIVERSION_AMDGPU_HSA_V6ELFABIVERSION_AMDGPU_PALELFABIVERSION_AMDGPU_MESA3De_ident[EI_CLASS]
: The ELF class is:
ELFCLASS32 for r600 architecture.ELFCLASS64 for amdgcn architecture which only supports 64-bit process address space applications.e_ident[EI_DATA]
: All AMDGPU targets use ELFDATA2LSB for little-endian byte ordering.
e_ident[EI_OSABI]
: One of the following AMDGPU target architecture specific OS ABIs (see {ref}amdgpu-os):
ELFOSABI_NONE for unknown OS.ELFOSABI_AMDGPU_HSA for amdhsa OS.ELFOSABI_AMDGPU_PAL for amdpal OS.ELFOSABI_AMDGPU_MESA3D for mesa3D OS.e_ident[EI_ABIVERSION]
: The ABI version of the AMDGPU target architecture specific OS ABI to which the code object conforms:
ELFABIVERSION_AMDGPU_HSA_V2 is used to specify the version of AMD HSA runtime ABI for code object V2. Can no longer be emitted by this version of LLVM.ELFABIVERSION_AMDGPU_HSA_V3 is used to specify the version of AMD HSA runtime ABI for code object V3. Can no longer be emitted by this version of LLVM.ELFABIVERSION_AMDGPU_HSA_V4 is used to specify the version of AMD HSA runtime ABI for code object V4. Specify using the Clang option -mcode-object-version=4.ELFABIVERSION_AMDGPU_HSA_V5 is used to specify the version of AMD HSA runtime ABI for code object V5. Specify using the Clang option -mcode-object-version=5. This is the default code object version if not specified.ELFABIVERSION_AMDGPU_HSA_V6 is used to specify the version of AMD HSA runtime ABI for code object V6. Specify using the Clang option -mcode-object-version=6.ELFABIVERSION_AMDGPU_PAL is used to specify the version of AMD PAL runtime ABI.ELFABIVERSION_AMDGPU_MESA3D is used to specify the version of AMD MESA 3D runtime ABI.e_type
: Can be one of the following values:
ET_REL
: The type produced by the AMDGPU backend compiler as it is relocatable code object.
ET_DYN
: The type produced by the linker as it is a shared code object.
The AMD HSA runtime loader requires a ET_DYN code object.
e_machine
: The value EM_AMDGPU is used for the machine for all processors supported by the r600 and amdgcn architectures (see {ref}amdgpu-processor-table). The specific processor is specified in the NT_AMD_HSA_ISA_VERSION note record for code object V2 (see {ref}amdgpu-note-records-v2) and in the EF_AMDGPU_MACH bit field of the e_flags for code object V3 and above (see {ref}amdgpu-elf-header-e_flags-table-v3, {ref}amdgpu-elf-header-e_flags-table-v4-v5 and {ref}amdgpu-elf-header-e_flags-table-v6-onwards).
e_entry
: The entry point is 0 as the entry points for individual kernels must be selected in order to invoke them through AQL packets.
e_flags
: The AMDGPU backend uses the following ELF header flags:
:::{list-table} AMDGPU ELF Header e_flags for Code Object V2 :name: amdgpu-elf-header-e_flags-v2-table :header-rows: 1
EF_AMDGPU_FEATURE_XNACK_V2xnack target feature is enabled for all code contained in the code object. If the processor does not support the xnack target feature then must be 0. See {ref}amdgpu-target-features.EF_AMDGPU_FEATURE_TRAP_HANDLER_V2amdgpu-target-features. ::::::{list-table} AMDGPU ELF Header e_flags for Code Object V3 :name: amdgpu-elf-header-e_flags-table-v3 :header-rows: 1
EF_AMDGPU_MACHEF_AMDGPU_MACH_xxx values defined in {ref}amdgpu-ef-amdgpu-mach-table.EF_AMDGPU_FEATURE_XNACK_V3xnack target feature is enabled for all code contained in the code object. If the processor does not support the xnack target feature then must be 0. See {ref}amdgpu-target-features.EF_AMDGPU_FEATURE_SRAMECC_V3sramecc target feature is enabled for all code contained in the code object. If the processor does not support the sramecc target feature then must be 0. See {ref}amdgpu-target-features. ::::::{list-table} AMDGPU ELF Header e_flags for Code Object V4 and V5 :name: amdgpu-elf-header-e_flags-table-v4-v5 :header-rows: 1
EF_AMDGPU_MACHEF_AMDGPU_MACH_xxx values defined in {ref}amdgpu-ef-amdgpu-mach-table.EF_AMDGPU_FEATURE_XNACK_V4EF_AMDGPU_FEATURE_XNACK_*_V4 values.EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4EF_AMDGPU_FEATURE_XNACK_ANY_V4EF_AMDGPU_FEATURE_XNACK_OFF_V4EF_AMDGPU_FEATURE_XNACK_ON_V4EF_AMDGPU_FEATURE_SRAMECC_V4EF_AMDGPU_FEATURE_SRAMECC_*_V4 values.EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4EF_AMDGPU_FEATURE_SRAMECC_ANY_V4EF_AMDGPU_FEATURE_SRAMECC_OFF_V4EF_AMDGPU_FEATURE_SRAMECC_ON_V4:::{list-table} AMDGPU ELF Header e_flags for Code Object V6 and After :name: amdgpu-elf-header-e_flags-table-v6-onwards :header-rows: 1
EF_AMDGPU_MACHEF_AMDGPU_MACH_xxx values defined in {ref}amdgpu-ef-amdgpu-mach-table.EF_AMDGPU_FEATURE_XNACK_V4EF_AMDGPU_FEATURE_XNACK_*_V4 values.EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4EF_AMDGPU_FEATURE_XNACK_ANY_V4EF_AMDGPU_FEATURE_XNACK_OFF_V4EF_AMDGPU_FEATURE_XNACK_ON_V4EF_AMDGPU_FEATURE_SRAMECC_V4EF_AMDGPU_FEATURE_SRAMECC_*_V4 values.EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4EF_AMDGPU_FEATURE_SRAMECC_ANY_V4EF_AMDGPU_FEATURE_SRAMECC_OFF_V4EF_AMDGPU_FEATURE_SRAMECC_ON_V4EF_AMDGPU_GENERIC_VERSION_Vamdgpu-generic-processor-versioning :::For code object V4 and later, processors with hardwired-on XNACK, such as gfx1250, use EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4 (zero) because they do not support mode selection. Their XNACK behavior is implied by EF_AMDGPU_MACH; a zero XNACK field does not mean replay is disabled on these processors.
For code object V4 and later, processors with hardwired-on SRAMECC use EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4 (zero) because they do not support mode selection. Their SRAMECC behavior is implied by EF_AMDGPU_MACH; a zero SRAMECC field does not mean SRAMECC is disabled on these processors.
:::{list-table} AMDGPU EF_AMDGPU_MACH Values :name: amdgpu-ef-amdgpu-mach-table :header-rows: 1 :widths: auto
amdgpu-processor-table)EF_AMDGPU_MACH_NONEEF_AMDGPU_MACH_R600_R600r600EF_AMDGPU_MACH_R600_R630r630EF_AMDGPU_MACH_R600_RS880rs880EF_AMDGPU_MACH_R600_RV670rv670EF_AMDGPU_MACH_R600_RV710rv710EF_AMDGPU_MACH_R600_RV730rv730EF_AMDGPU_MACH_R600_RV770rv770EF_AMDGPU_MACH_R600_CEDARcedarEF_AMDGPU_MACH_R600_CYPRESScypressEF_AMDGPU_MACH_R600_JUNIPERjuniperEF_AMDGPU_MACH_R600_REDWOODredwoodEF_AMDGPU_MACH_R600_SUMOsumoEF_AMDGPU_MACH_R600_BARTSbartsEF_AMDGPU_MACH_R600_CAICOScaicosEF_AMDGPU_MACH_R600_CAYMANcaymanEF_AMDGPU_MACH_R600_TURKSturksr600 architecture processors.EF_AMDGPU_MACH_AMDGCN_GFX600gfx600EF_AMDGPU_MACH_AMDGCN_GFX601gfx601EF_AMDGPU_MACH_AMDGCN_GFX700gfx700EF_AMDGPU_MACH_AMDGCN_GFX701gfx701EF_AMDGPU_MACH_AMDGCN_GFX702gfx702EF_AMDGPU_MACH_AMDGCN_GFX703gfx703EF_AMDGPU_MACH_AMDGCN_GFX704gfx704EF_AMDGPU_MACH_AMDGCN_GFX801gfx801EF_AMDGPU_MACH_AMDGCN_GFX802gfx802EF_AMDGPU_MACH_AMDGCN_GFX803gfx803EF_AMDGPU_MACH_AMDGCN_GFX810gfx810EF_AMDGPU_MACH_AMDGCN_GFX900gfx900EF_AMDGPU_MACH_AMDGCN_GFX902gfx902EF_AMDGPU_MACH_AMDGCN_GFX904gfx904EF_AMDGPU_MACH_AMDGCN_GFX906gfx906EF_AMDGPU_MACH_AMDGCN_GFX908gfx908EF_AMDGPU_MACH_AMDGCN_GFX909gfx909EF_AMDGPU_MACH_AMDGCN_GFX90Cgfx90cEF_AMDGPU_MACH_AMDGCN_GFX1010gfx1010EF_AMDGPU_MACH_AMDGCN_GFX1011gfx1011EF_AMDGPU_MACH_AMDGCN_GFX1012gfx1012EF_AMDGPU_MACH_AMDGCN_GFX1030gfx1030EF_AMDGPU_MACH_AMDGCN_GFX1031gfx1031EF_AMDGPU_MACH_AMDGCN_GFX1032gfx1032EF_AMDGPU_MACH_AMDGCN_GFX1033gfx1033EF_AMDGPU_MACH_AMDGCN_GFX602gfx602EF_AMDGPU_MACH_AMDGCN_GFX705gfx705EF_AMDGPU_MACH_AMDGCN_GFX805gfx805EF_AMDGPU_MACH_AMDGCN_GFX1035gfx1035EF_AMDGPU_MACH_AMDGCN_GFX1034gfx1034EF_AMDGPU_MACH_AMDGCN_GFX90Agfx90aEF_AMDGPU_MACH_AMDGCN_GFX1100gfx1100EF_AMDGPU_MACH_AMDGCN_GFX1013gfx1013EF_AMDGPU_MACH_AMDGCN_GFX1150gfx1150EF_AMDGPU_MACH_AMDGCN_GFX1103gfx1103EF_AMDGPU_MACH_AMDGCN_GFX1036gfx1036EF_AMDGPU_MACH_AMDGCN_GFX1101gfx1101EF_AMDGPU_MACH_AMDGCN_GFX1102gfx1102EF_AMDGPU_MACH_AMDGCN_GFX1200gfx1200EF_AMDGPU_MACH_AMDGCN_GFX1250gfx1250EF_AMDGPU_MACH_AMDGCN_GFX1151gfx1151EF_AMDGPU_MACH_AMDGCN_GFX942gfx942EF_AMDGPU_MACH_AMDGCN_GFX1201gfx1201EF_AMDGPU_MACH_AMDGCN_GFX950gfx950EF_AMDGPU_MACH_AMDGCN_GFX1310gfx1310EF_AMDGPU_MACH_AMDGCN_GFX9_GENERICgfx9-genericEF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERICgfx10-1-genericEF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERICgfx10-3-genericEF_AMDGPU_MACH_AMDGCN_GFX11_GENERICgfx11-genericEF_AMDGPU_MACH_AMDGCN_GFX1152gfx1152.EF_AMDGPU_MACH_AMDGCN_GFX1154gfx1154.EF_AMDGPU_MACH_AMDGCN_GFX1153gfx1153.EF_AMDGPU_MACH_AMDGCN_GFX12_GENERICgfx12-genericEF_AMDGPU_MACH_AMDGCN_GFX1251gfx1251EF_AMDGPU_MACH_AMDGCN_GFX12_5_GENERICgfx12-5-genericEF_AMDGPU_MACH_AMDGCN_GFX1172gfx1172EF_AMDGPU_MACH_AMDGCN_GFX1170gfx1170EF_AMDGPU_MACH_AMDGCN_GFX1171gfx1171EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERICgfx9-4-genericEF_AMDGPU_MACH_AMDGCN_GFX11_7_GENERICgfx11-7-genericEF_AMDGPU_MACH_AMDGCN_GFX13_GENERICgfx13-genericEF_AMDGPU_MACH_AMDGCN_GFX1250_STRICTgfx1250-strict :::An AMDGPU target ELF code object has the standard ELF sections which include:
:::{list-table} AMDGPU ELF Sections :name: amdgpu-elf-sections-table :header-rows: 1 :widths: auto
.bssSHT_NOBITSSHF_ALLOC + SHF_WRITE.dataSHT_PROGBITSSHF_ALLOC + SHF_WRITE.debug_*SHT_PROGBITS.dynamicSHT_DYNAMICSHF_ALLOC.dynstrSHT_PROGBITSSHF_ALLOC.dynsymSHT_PROGBITSSHF_ALLOC.gotSHT_PROGBITSSHF_ALLOC + SHF_WRITE.hashSHT_HASHSHF_ALLOC.noteSHT_NOTE.relanameSHT_RELA.rela.dynSHT_RELA.rodataSHT_PROGBITSSHF_ALLOC.shstrtabSHT_STRTAB.strtabSHT_STRTAB.symtabSHT_SYMTAB.textSHT_PROGBITSSHF_ALLOC + SHF_EXECINSTR.amdgpu.infoSHT_PROGBITSSHF_EXCLUDE.amdgpu.strtabSHT_STRTABSHF_EXCLUDE :::These sections have their standard meanings (see [{ref}ELF <elf>]) and are only generated if needed.
.debug*
: The standard DWARF sections. See {ref}amdgpu-dwarf-debug-information for information on the DWARF produced by the AMDGPU backend.
.dynamic, .dynstr, .dynsym, .hash
: The standard sections used by a dynamic loader.
.note
: See {ref}amdgpu-note-records for the note records supported by the AMDGPU backend.
.relaname, .rela.dyn
: For relocatable code objects, name is the name of the section that the relocation records apply. For example, .rela.text is the section name for relocation records associated with the .text section.
For linked shared code objects, .rela.dyn contains all the relocation records from each of the relocatable code object's .relaname sections.
See {ref}amdgpu-relocation-records for the relocation records supported by the AMDGPU backend.
.text
: The executable machine code for the kernels and functions they call. Generated as position independent code. See {ref}amdgpu-code-conventions for information on conventions used in the isa generation.
.amdgpu.kernel.runtime.handle
: Symbols used for device enqueue.
(amdgpu-info-section)=
.amdgpu.info
: Per-function metadata for AMDGPU object linking, emitted only in relocatable code objects when object linking is enabled (-amdgpu-enable-object-linking). The linker uses this section to propagate resource usage (registers, stack, LDS) and resolve call graph dependencies across translation units.
Each entry uses a tagged, length-prefixed binary encoding:
[kind: u8] [len: u8] [payload: <len> bytes]
A function scope is opened by an INFO_FUNC entry whose payload is an 8-byte relocated symbol reference. All subsequent entries until the next INFO_FUNC or end of section belong to that scope. The format is forward-compatible: unknown kinds can be skipped by reading the length byte.
:::{list-table} AMDGPU Info Entry Kinds :name: amdgpu-info-entry-kinds-table :header-rows: 1
INFO_FUNCINFO_FLAGSFuncInfoFlags bitfieldINFO_NUM_SGPRINFO_NUM_VGPRINFO_NUM_AGPRINFO_PRIVATE_SEGMENT_SIZEINFO_USEINFO_CALLINFO_INDIRECT_CALLINFO_TYPEID:::{list-table} AMDGPU Info Function Flags (INFO_FLAGS) :name: amdgpu-info-flags-table :header-rows: 1
FUNC_USES_VCCFUNC_USES_FLAT_SCRATCHFUNC_HAS_DYN_STACKSymbol references (INFO_FUNC, INFO_USE, INFO_CALL) generate R_AMDGPU_ABS64 relocations in .rela.amdgpu.info. String payloads (INFO_INDIRECT_CALL, INFO_TYPEID) store a u32 offset into the companion .amdgpu.strtab section.
See {ref}amdgpu-assembler-directive-amdgpu-info for the assembly syntax.
.amdgpu.strtab
: Null-terminated string pool for the .amdgpu.info section. Contains type-ID strings referenced by INFO_INDIRECT_CALL and INFO_TYPEID entries. Only present when .amdgpu.info requires string data.
(amdgpu-note-records)=
The AMDGPU backend code object contains ELF note records in the .note section. The set of generated notes and their semantics depend on the code object version; see {ref}amdgpu-note-records-v2 and {ref}amdgpu-note-records-v3-onwards.
As required by ELFCLASS32 and ELFCLASS64, minimal zero-byte padding must be generated after the name field to ensure the desc field is 4 byte aligned. In addition, minimal zero-byte padding must be generated to ensure the desc field size is a multiple of 4 bytes. The sh_addralign field of the .note section must be at least 4 to indicate at least 8 byte alignment.
(amdgpu-note-records-v2)=
:::{warning} Code object V2 generation is no longer supported by this version of LLVM. :::
The AMDGPU backend code object uses the following ELF note record in the .note section when compiling for code object V2.
The note record vendor field is “AMD”.
Additional note records may be present, but any which are not documented here are deprecated and should not be used.
:::{list-table} AMDGPU Code Object V2 ELF Note Records :name: amdgpu-elf-note-records-v2-table :header-rows: 1 :widths: auto
NT_AMD_HSA_CODE_OBJECT_VERSIONNT_AMD_HSA_HSAILNT_AMD_HSA_ISA_VERSIONNT_AMD_HSA_METADATAYAML <yaml>] textual format.NT_AMD_HSA_ISA_NAME%
:::{list-table} AMDGPU Code Object V2 ELF Note Record Enumeration Values :name: amdgpu-elf-note-record-enumeration-values-v2-table :header-rows: 1 :widths: auto
NT_AMD_HSA_CODE_OBJECT_VERSIONNT_AMD_HSA_HSAILNT_AMD_HSA_ISA_VERSIONNT_AMD_HSA_METADATANT_AMD_HSA_ISA_NAMENT_AMD_HSA_CODE_OBJECT_VERSION
: Specifies the code object version number. The description field has the following layout:
struct amdgpu_hsa_note_code_object_version_s { uint32_t major_version; uint32_t minor_version; };
The major_version has a value less than or equal to 2.
NT_AMD_HSA_HSAIL
: Specifies the HSAIL properties used by the HSAIL Finalizer. The description field has the following layout:
struct amdgpu_hsa_note_hsail_s { uint32_t hsail_major_version; uint32_t hsail_minor_version; uint8_t profile; uint8_t machine_model; uint8_t default_float_round; };
NT_AMD_HSA_ISA_VERSION
: Specifies the target ISA version. The description field has the following layout:
struct amdgpu_hsa_note_isa_s { uint16_t vendor_name_size; uint16_t architecture_name_size; uint32_t major; uint32_t minor; uint32_t stepping; char vendor_and_architecture_name[1]; };
vendor_name_size and architecture_name_size are the length of the vendor and architecture names respectively, including the NUL character.
vendor_and_architecture_name contains the NUL terminated string for the vendor, immediately followed by the NUL terminated string for the architecture.
This note record is used by the HSA runtime loader.
Code object V2 only supports a limited number of processors and has fixed settings for target features. See {ref}amdgpu-elf-note-record-supported_processors-v2-table for a list of processors and the corresponding target ID. In the table the note record ISA name is a concatenation of the vendor name, architecture name, major, minor, and stepping separated by a “:”.
The target ID column shows the processor name and fixed target features used by the LLVM compiler. The LLVM compiler does not generate a NT_AMD_HSA_HSAIL note record.
A code object generated by the Finalizer also uses code object V2 and always generates a NT_AMD_HSA_HSAIL note record. The processor name and sramecc target feature is as shown in {ref}amdgpu-elf-note-record-supported_processors-v2-table but the xnack target feature is specified by the EF_AMDGPU_FEATURE_XNACK_V2 e_flags bit.
NT_AMD_HSA_ISA_NAME
: Specifies the target ISA name as a non-NUL terminated string.
This note record is not used by the HSA runtime loader.
See the NT_AMD_HSA_ISA_VERSION note record description of the code object V2's limited support of processors and fixed settings for target features.
See {ref}amdgpu-elf-note-record-supported_processors-v2-table for a mapping from the string to the corresponding target ID. If the xnack target feature is supported and enabled, the string produced by the LLVM compiler will may have a +xnack appended. The Finlizer did not do the appending and instead used the EF_AMDGPU_FEATURE_XNACK_V2 e_flags bit.
NT_AMD_HSA_METADATA
: Specifies extensible metadata associated with the code objects executed on HSA [{ref}HSA <hsa>] compatible runtimes (see {ref}amdgpu-os). It is required when the target triple OS is amdhsa (see {ref}amdgpu-target-triples). See {ref}amdgpu-amdhsa-code-object-metadata-v2 for the syntax of the code object metadata string.
:::{list-table} AMDGPU Code Object V2 Supported Processors and Fixed Target Feature Settings :name: amdgpu-elf-note-record-supported_processors-v2-table :header-rows: 1
AMD:AMDGPU:6:0:0gfx600AMD:AMDGPU:6:0:1gfx601AMD:AMDGPU:6:0:2gfx602AMD:AMDGPU:7:0:0gfx700AMD:AMDGPU:7:0:1gfx701AMD:AMDGPU:7:0:2gfx702AMD:AMDGPU:7:0:3gfx703AMD:AMDGPU:7:0:4gfx704AMD:AMDGPU:7:0:5gfx705AMD:AMDGPU:8:0:0gfx802AMD:AMDGPU:8:0:1gfx801:xnack+AMD:AMDGPU:8:0:2gfx802AMD:AMDGPU:8:0:3gfx803AMD:AMDGPU:8:0:4gfx803AMD:AMDGPU:8:0:5gfx805AMD:AMDGPU:8:1:0gfx810:xnack+AMD:AMDGPU:9:0:0gfx900:xnack-AMD:AMDGPU:9:0:1gfx900:xnack+AMD:AMDGPU:9:0:2gfx902:xnack-AMD:AMDGPU:9:0:3gfx902:xnack+AMD:AMDGPU:9:0:4gfx904:xnack-AMD:AMDGPU:9:0:5gfx904:xnack+AMD:AMDGPU:9:0:6gfx906:sramecc-:xnack-AMD:AMDGPU:9:0:7gfx906:sramecc-:xnack+AMD:AMDGPU:9:0:12gfx90c:xnack- :::(amdgpu-note-records-v3-onwards)=
The AMDGPU backend code object uses the following ELF note record in the .note section when compiling for code object V3 and above.
The note record vendor field is “AMDGPU”.
Additional note records may be present, but any which are not documented here are deprecated and should not be used.
:::{list-table} AMDGPU Code Object V3 and Above ELF Note Records :name: amdgpu-elf-note-records-table-v3-onwards :header-rows: 1 :widths: auto
NT_AMDGPU_METADATAMsgPack <msgpack>] binary format.NT_AMDGPU_KFD_CORE_STATEamdgpu_corefile_note. :::%
:::{list-table} AMDGPU Code Object V3 and Above ELF Note Record Enumeration Values :name: amdgpu-elf-note-record-enumeration-values-table-v3-onwards :header-rows: 1 :widths: auto
NT_AMDGPU_METADATANT_AMDGPU_KFD_CORE_STATENT_AMDGPU_METADATA
: Specifies extensible metadata associated with an AMDGPU code object. It is encoded as a map in the Message Pack [{ref}MsgPack <msgpack>] binary data format. See {ref}amdgpu-amdhsa-code-object-metadata-v3, {ref}amdgpu-amdhsa-code-object-metadata-v4 and {ref}amdgpu-amdhsa-code-object-metadata-v5 for the map keys defined for the amdhsa OS.
(amdgpu-symbols)=
Symbols include the following:
:::{list-table} AMDGPU ELF Symbols :name: amdgpu-elf-symbols-table :header-rows: 1 :widths: auto
STT_OBJECT.data.rodata.bss.kdSTT_OBJECT.rodataSTT_FUNC.textSTT_OBJECTGlobal variable
: Global variables both used and defined by the compilation unit.
If the symbol is defined in the compilation unit then it is allocated in the appropriate section according to if it has initialized data or is readonly.
If the symbol is external then its section is STN_UNDEF and the loader will resolve relocations using the definition provided by another code object or explicitly defined by the runtime.
If the symbol resides in local/group memory (LDS) then its section is the special processor specific section name SHN_AMDGPU_LDS, and the st_value field describes alignment requirements as it does for common symbols.
:::{todo} Add description of linked shared object symbols. Seems undefined symbols are marked as STT_NOTYPE. :::
Kernel descriptor
: Every HSA kernel has an associated kernel descriptor. It is the address of the kernel descriptor that is used in the AQL dispatch packet used to invoke the kernel, not the kernel entry point. The layout of the HSA kernel descriptor is defined in {ref}amdgpu-amdhsa-kernel-descriptor.
Kernel entry point
: Every HSA kernel also has a symbol for its machine code entry point.
(amdgpu-relocation-records)=
The AMDGPU backend generates Elf64_Rela relocation records for AMDHSA or Elf64_Rel relocation records for Mesa/AMDPAL. Supported relocatable fields are:
word32
: This specifies a 32-bit field occupying 4 bytes with arbitrary byte alignment. These values use the same byte order as other word values in the AMDGPU architecture.
word64
: This specifies a 64-bit field occupying 8 bytes with arbitrary byte alignment. These values use the same byte order as other word values in the AMDGPU architecture.
Following notations are used for specifying relocation calculations:
A
: Represents the addend used to compute the value of the relocatable field. If the addend field is smaller than 64 bits then it is zero-extended to 64 bits for use in the calculations below. (In practice this only affects _HI relocation types on Mesa/AMDPAL, where the addend comes from the 32-bit field but the result of the calculation depends on the high part of the full 64-bit address.)
G
: Represents the offset into the global offset table at which the relocation entry's symbol will reside during execution.
GOT
: Represents the address of the global offset table.
P
: Represents the place (section offset for et_rel or address for et_dyn) of the storage unit being relocated (computed using r_offset).
S
: Represents the value of the symbol whose index resides in the relocation entry. Relocations not using this must specify a symbol index of STN_UNDEF.
B
: Represents the base address of a loaded executable or shared object which is the difference between the ELF address and the actual load address. Relocations using this are only valid in executable or shared objects.
The following relocation types are supported:
:::{list-table} AMDGPU ELF Relocation Records :name: amdgpu-elf-relocation-records-table :header-rows: 1 :widths: auto
R_AMDGPU_NONER_AMDGPU_ABS32_LOword32R_AMDGPU_ABS32_HIword32R_AMDGPU_ABS64word64R_AMDGPU_REL32word32R_AMDGPU_REL64word64R_AMDGPU_ABS32word32R_AMDGPU_GOTPCRELword32R_AMDGPU_GOTPCREL32_LOword32R_AMDGPU_GOTPCREL32_HIword32R_AMDGPU_REL32_LOword32R_AMDGPU_REL32_HIword32R_AMDGPU_RELATIVE64word64R_AMDGPU_REL16word16R_AMDGPU_ABS32_LO and R_AMDGPU_ABS32_HI are only supported by the mesa3d OS, which does not support R_AMDGPU_ABS64.
There is no current OS loader support for 32-bit programs and so R_AMDGPU_ABS32 is only generated for static relocations, for example to implement some DWARF32 forms.
(amdgpu-loaded-code-object-path-uniform-resource-identifier)=
The AMD GPU code object loader represents the path of the ELF shared object from which the code object was loaded as a textual Uniform Resource Identifier (URI). Note that the code object is the in memory loaded relocated form of the ELF shared object. Multiple code objects may be loaded at different memory addresses in the same process from the same ELF shared object.
The loaded code object path URI syntax is defined by the following BNF syntax:
code_object_uri ::== file_uri | memory_uri file_uri ::== "file://" file_path [ range_specifier ] memory_uri ::== "memory://" process_id range_specifier range_specifier ::== [ "#" | "?" ] "offset=" number "&" "size=" number file_path ::== URI_ENCODED_OS_FILE_PATH process_id ::== DECIMAL_NUMBER number ::== HEX_NUMBER | DECIMAL_NUMBER | OCTAL_NUMBER
number
: Is a C integral literal where hexadecimal values are prefixed by “0x” or “0X”, and octal values by “0”.
file_path
: Is the file's path specified as a URI encoded UTF-8 string. In URI encoding, every character that is not in the regular expression [a-zA-Z0-9/_.~-] is encoded as two uppercase hexadecimal digits proceeded by “%”. Directories in the path are separated by “/”.
offset
: Is a 0-based byte offset to the start of the code object. For a file URI, it is from the start of the file specified by the file_path, and if omitted defaults to 0. For a memory URI, it is the memory address and is required.
size
: Is the number of bytes in the code object. For a file URI, if omitted it defaults to the size of the file. It is required for a memory URI.
process_id
: Is the identity of the process owning the memory. For Linux it is the C unsigned integral decimal literal for the process ID (PID).
For example:
file:///dir1/dir2/file1 file:///dir3/dir4/file2#offset=0x2000&size=3000 memory://1234#offset=0x20000&size=3000
(amdgpu-dwarf-debug-information)=
:::{warning} This section describes provisional support for AMDGPU DWARF [{ref}DWARF <dwarf>] that is not currently fully implemented and is subject to change. :::
AMDGPU generates DWARF [{ref}DWARF <dwarf>] debugging information ELF sections (see {ref}amdgpu-elf-code-object) which contain information that maps the code object executable code and data to the source language constructs. It can be used by tools such as debuggers and profilers. It uses features defined in DWARF Extensions For Heterogeneous Debugging that are made available in DWARF Version 4 and DWARF Version 5 as an LLVM vendor extension.
This section defines the AMDGPU target architecture specific DWARF mappings.
(amdgpu-dwarf-register-identifier)=
This section defines the AMDGPU target architecture register numbers used in DWARF operation expressions (see DWARF Version 5 section 2.5 and {ref}amdgpu-dwarf-operation-expressions) and Call Frame Information instructions (see DWARF Version 5 section 6.4 and {ref}amdgpu-dwarf-call-frame-information).
A single code object can contain code for kernels that have different wavefront sizes. The vector registers and some scalar registers are based on the wavefront size. AMDGPU defines distinct DWARF registers for each wavefront size. This simplifies the consumer of the DWARF so that each register has a fixed size, rather than being dynamic according to the wavefront size mode. Similarly, distinct DWARF registers are defined for those registers that vary in size according to the process address size. This allows a consumer to treat a specific AMDGPU processor as a single architecture regardless of how it is configured at run time. The compiler explicitly specifies the DWARF registers that match the mode in which the code it is generating will be executed.
DWARF registers are encoded as numbers, which are mapped to architecture registers. The mapping for AMDGPU is defined in {ref}amdgpu-dwarf-register-mapping-table. All AMDGPU targets use the same mapping.
:::{list-table} AMDGPU DWARF Register Mapping :name: amdgpu-dwarf-register-mapping-table :header-rows: 1 :widths: auto
The vector registers are represented as the full size for the wavefront. They are organized as consecutive dwords (32-bits), one per lane, with the dword at the least significant bit position corresponding to lane 0 and so forth. DWARF location expressions involving the DW_OP_LLVM_offset and DW_OP_LLVM_push_lane operations are used to select the part of the vector register corresponding to the lane that is executing the current thread of execution in languages that are implemented using a SIMD or SIMT execution model.
If the wavefront size is 32 lanes then the wavefront 32 mode register definitions are used. If the wavefront size is 64 lanes then the wavefront 64 mode register definitions are used. Some AMDGPU targets support executing in both wavefront 32 and wavefront 64 mode. The register definitions corresponding to the wavefront mode of the generated code will be used.
If code is generated to execute in a 32-bit process address space, then the 32-bit process address space register definitions are used. If code is generated to execute in a 64-bit process address space, then the 64-bit process address space register definitions are used. The amdgcn target only supports the 64-bit process address space.
(amdgpu-dwarf-memory-space-identifier)=
The DWARF memory space represents the source language memory space. See DWARF Version 5 section 2.12 which is updated by the DWARF Extensions For Heterogeneous Debugging section {ref}amdgpu-dwarf-memory-spaces.
The DWARF memory space mapping used for AMDGPU is defined in {ref}amdgpu-dwarf-memory-space-mapping-table.
:::{list-table} AMDGPU DWARF Memory Space Mapping :name: amdgpu-dwarf-memory-space-mapping-table :header-rows: 2 :widths: auto
DW_MSPACE_LLVM_noneDW_MSPACE_LLVM_globalDW_MSPACE_LLVM_constantDW_MSPACE_LLVM_groupDW_MSPACE_LLVM_privateDW_MSPACE_AMDGPU_regionThe DWARF memory space values defined in the DWARF Extensions For Heterogeneous Debugging section {ref}amdgpu-dwarf-memory-spaces are used.
In addition, DW_ADDR_AMDGPU_region is encoded as a vendor extension. This is available for use for the AMD extension for access to the hardware GDS memory which is scratchpad memory allocated per device.
For AMDGPU if no DW_AT_LLVM_memory_space attribute is present, then the default memory space of DW_MSPACE_LLVM_none is used.
See {ref}amdgpu-dwarf-address-space-identifier for information on the AMDGPU mapping of DWARF memory spaces to DWARF address spaces, including address size and NULL value.
(amdgpu-dwarf-address-space-identifier)=
DWARF address spaces correspond to target architecture specific linear addressable memory areas. See DWARF Version 5 section 2.12 and DWARF Extensions For Heterogeneous Debugging section {ref}amdgpu-dwarf-address-spaces.
The DWARF address space mapping used for AMDGPU is defined in {ref}amdgpu-dwarf-address-space-mapping-table.
:::{list-table} AMDGPU DWARF Address Space Mapping :name: amdgpu-dwarf-address-space-mapping-table :header-rows: 3 :widths: auto
DW_ASPACE_LLVM_noneDW_ASPACE_AMDGPU_genericDW_ASPACE_AMDGPU_regionDW_ASPACE_AMDGPU_localDW_ASPACE_AMDGPU_private_laneDW_ASPACE_AMDGPU_private_waveSee {ref}amdgpu-address-spaces for information on the AMDGPU LLVM IR address spaces including address size and NULL value.
The DW_ASPACE_LLVM_none address space is the default target architecture address space used in DWARF operations that do not specify an address space. It therefore has to map to the global address space so that the DW_OP_addr* and related operations can refer to addresses in the program code.
The DW_ASPACE_AMDGPU_generic address space allows location expressions to specify the flat address space. If the address corresponds to an address in the local address space, then it corresponds to the wavefront that is executing the focused thread of execution. If the address corresponds to an address in the private address space, then it corresponds to the lane that is executing the focused thread of execution for languages that are implemented using a SIMD or SIMT execution model.
:::{note} CUDA-like languages such as HIP that do not have address spaces in the language type system, but do allow variables to be allocated in different address spaces, need to explicitly specify the DW_ASPACE_AMDGPU_generic address space in the DWARF expression operations as the default address space is the global address space. :::
The DW_ASPACE_AMDGPU_local address space allows location expressions to specify the local address space corresponding to the wavefront that is executing the focused thread of execution.
The DW_ASPACE_AMDGPU_private_lane address space allows location expressions to specify the private address space corresponding to the lane that is executing the focused thread of execution for languages that are implemented using a SIMD or SIMT execution model.
The DW_ASPACE_AMDGPU_private_wave address space allows location expressions to specify the unswizzled private address space corresponding to the wavefront that is executing the focused thread of execution. The wavefront view of private memory is the per wavefront unswizzled backing memory layout defined in {ref}amdgpu-address-spaces, such that address 0 corresponds to the first location for the backing memory of the wavefront (namely the address is not offset by wavefront-scratch-base). The following formula can be used to convert from a DW_ASPACE_AMDGPU_private_lane address to a DW_ASPACE_AMDGPU_private_wave address:
private-address-wavefront = ((private-address-lane / 4) * wavefront-size * 4) + (wavefront-lane-id * 4) + (private-address-lane % 4)
If the DW_ASPACE_AMDGPU_private_lane address is dword aligned, and the start of the dwords for each lane starting with lane 0 is required, then this simplifies to:
private-address-wavefront = private-address-lane * wavefront-size
A compiler can use the DW_ASPACE_AMDGPU_private_wave address space to read a complete spilled vector register back into a complete vector register in the CFI. The frame pointer can be a private lane address which is dword aligned, which can be shifted to multiply by the wavefront size, and then used to form a private wavefront address that gives a location for a contiguous set of dwords, one per lane, where the vector register dwords are spilled. The compiler knows the wavefront size since it generates the code. Note that the type of the address may have to be converted as the size of a DW_ASPACE_AMDGPU_private_lane address may be smaller than the size of a DW_ASPACE_AMDGPU_private_wave address.
(amdgpu-dwarf-lane-identifier)=
DWARF lane identifies specify a target architecture lane position for hardware that executes in a SIMD or SIMT manner, and on which a source language maps its threads of execution onto those lanes. The DWARF lane identifier is pushed by the DW_OP_LLVM_push_lane DWARF expression operation. See DWARF Version 5 section 2.5 which is updated by DWARF Extensions For Heterogeneous Debugging section {ref}amdgpu-dwarf-operation-expressions.
For AMDGPU, the lane identifier corresponds to the hardware lane ID of a wavefront. It is numbered from 0 to the wavefront size minus 1.
DWARF expressions are used to compute program values and the locations of program objects. See DWARF Version 5 section 2.5 and {ref}amdgpu-dwarf-operation-expressions.
DWARF location descriptions describe how to access storage which includes memory and registers. When accessing storage on AMDGPU, bytes are ordered with least significant bytes first, and bits are ordered within bytes with least significant bits first.
For AMDGPU CFI expressions, DW_OP_LLVM_select_bit_piece is used to describe unwinding vector registers that are spilled under the execution mask to memory: the zero-single location description is the vector register, and the one-single location description is the spilled memory location description. The DW_OP_LLVM_form_aspace_address is used to specify the address space of the memory location description.
In AMDGPU expressions, DW_OP_LLVM_select_bit_piece is used by the DW_AT_LLVM_lane_pc attribute expression where divergent control flow is controlled by the execution mask. An undefined location description together with DW_OP_LLVM_extend is used to indicate the lane was not active on entry to the subprogram. See {ref}amdgpu-dwarf-dw-at-llvm-lane-pc for an example.
(amdgpu-dwarf-base-type-conversions)=
For AMDGPU expressions, DW_OP_convert may be used to convert between DW_ATE_address-encoded base types in different address spaces.
Conversions are defined as in {ref}amdgpu-address-spaces when all relevant conditions described there are met, and otherwise result in an evaluation error.
:::{note} For a target which does not support a particular address space, converting to or from that address space is always an evaluation error.
For targets which support the generic address space, converting from DW_ASPACE_AMDGPU_generic to DW_ASPACE_LLVM_none is defined when the generic address is in the global address space. The conversion requires no change to the literal value of the address.
Converting from DW_ASPACE_AMDGPU_generic to any of DW_ASPACE_AMDGPU_local, DW_ASPACE_AMDGPU_private_wave or DW_ASPACE_AMDGPU_private_lane is defined when the relevant hardware support is present, any required hardware setup has been completed, and the generic address is in the corresponding address space. Conversion to DW_ASPACE_AMDGPU_private_lane additionally requires the context to include the active lane. :::
This section describes how certain debugger information entry attributes are used by AMDGPU. See the sections in DWARF Version 5 section 3.3.5 and 3.1.1 which are updated by DWARF Extensions For Heterogeneous Debugging section {ref}amdgpu-dwarf-low-level-information and {ref}amdgpu-dwarf-full-and-partial-compilation-unit-entries.
(amdgpu-dwarf-dw-at-llvm-lane-pc)=
DW_AT_LLVM_lane_pcFor AMDGPU, the DW_AT_LLVM_lane_pc attribute is used to specify the program location of the separate lanes of a SIMT thread.
If the lane is an active lane then this will be the same as the current program location.
If the lane is inactive, but was active on entry to the subprogram, then this is the program location in the subprogram at which execution of the lane is conceptually positioned.
If the lane was not active on entry to the subprogram, then this will be the undefined location. A client debugger can check if the lane is part of a valid work-group by checking that the lane is in the range of the associated work-group within the grid, accounting for partial work-groups. If it is not, then the debugger can omit any information for the lane. Otherwise, the debugger may repeatedly unwind the stack and inspect the DW_AT_LLVM_lane_pc of the calling subprogram until it finds a non-undefined location. Conceptually the lane only has the call frames that it has a non-undefined DW_AT_LLVM_lane_pc.
The following example illustrates how the AMDGPU backend can generate a DWARF location list expression for the nested IF/THEN/ELSE structures of the following subprogram pseudo code for a target with 64 lanes per wavefront.
:number-lines: SUBPROGRAM X BEGIN a; IF (c1) THEN b; IF (c2) THEN c; ELSE d; ENDIF e; ELSE f; ENDIF g; END
The AMDGPU backend may generate the following pseudo LLVM MIR to manipulate the execution mask (EXEC) to linearize the control flow. The condition is evaluated to make a mask of the lanes for which the condition evaluates to true. First the THEN region is executed by setting the EXEC mask to the logical AND of the current EXEC mask with the condition mask. Then the ELSE region is executed by negating the EXEC mask and logical AND of the saved EXEC mask at the start of the region. After the IF/THEN/ELSE region the EXEC mask is restored to the value it had at the beginning of the region. This is shown below. Other approaches are possible, but the basic concept is the same.
:number-lines: $lex_start: a; %1 = EXEC %2 = c1 $lex_1_start: EXEC = %1 & %2 $if_1_then: b; %3 = EXEC %4 = c2 $lex_1_1_start: EXEC = %3 & %4 $lex_1_1_then: c; EXEC = ~EXEC & %3 $lex_1_1_else: d; EXEC = %3 $lex_1_1_end: e; EXEC = ~EXEC & %1 $lex_1_else: f; EXEC = %1 $lex_1_end: g; $lex_end:
To create the DWARF location list expression that defines the location description of a vector of lane program locations, the LLVM MIR DBG_VALUE pseudo instruction can be used to annotate the linearized control flow. This can be done by defining an artificial variable for the lane PC. The DWARF location list expression created for it is used as the value of the DW_AT_LLVM_lane_pc attribute on the subprogram's debugger information entry.
A DWARF procedure is defined for each well nested structured control flow region which provides the conceptual lane program location for a lane if it is not active (namely it is divergent). The DWARF operation expression for each region conceptually inherits the value of the immediately enclosing region and modifies it according to the semantics of the region.
For an IF/THEN/ELSE region the divergent program location is at the start of the region for the THEN region since it is executed first. For the ELSE region the divergent program location is at the end of the IF/THEN/ELSE region since the THEN region has completed.
The lane PC artificial variable is assigned at each region transition. It uses the immediately enclosing region's DWARF procedure to compute the program location for each lane assuming they are divergent, and then modifies the result by inserting the current program location for each lane that the EXEC mask indicates is active.
By having separate DWARF procedures for each region, they can be reused to define the value for any nested region. This reduces the total size of the DWARF operation expressions.
The following provides an example using pseudo LLVM MIR.
:number-lines: $lex_start: DEFINE_DWARF %__uint_64 = DW_TAG_base_type[ DW_AT_name = "__uint64"; DW_AT_byte_size = 8; DW_AT_encoding = DW_ATE_unsigned; ]; DEFINE_DWARF %__active_lane_pc = DW_TAG_dwarf_procedure[ DW_AT_name = "__active_lane_pc"; DW_AT_location = [ DW_OP_regx PC; DW_OP_LLVM_extend 64, 64; DW_OP_regval_type EXEC, %uint_64; DW_OP_LLVM_select_bit_piece 64, 64; ]; ]; DEFINE_DWARF %__divergent_lane_pc = DW_TAG_dwarf_procedure[ DW_AT_name = "__divergent_lane_pc"; DW_AT_location = [ DW_OP_LLVM_undefined; DW_OP_LLVM_extend 64, 64; ]; ]; DBG_VALUE $noreg, $noreg, %DW_AT_LLVM_lane_pc, DIExpression[ DW_OP_call_ref %__divergent_lane_pc; DW_OP_call_ref %__active_lane_pc; ]; a; %1 = EXEC; DBG_VALUE %1, $noreg, %__lex_1_save_exec; %2 = c1; $lex_1_start: EXEC = %1 & %2; $lex_1_then: DEFINE_DWARF %__divergent_lane_pc_1_then = DW_TAG_dwarf_procedure[ DW_AT_name = "__divergent_lane_pc_1_then"; DW_AT_location = DIExpression[ DW_OP_call_ref %__divergent_lane_pc; DW_OP_addrx &lex_1_start; DW_OP_stack_value; DW_OP_LLVM_extend 64, 64; DW_OP_call_ref %__lex_1_save_exec; DW_OP_deref_type 64, %__uint_64; DW_OP_LLVM_select_bit_piece 64, 64; ]; ]; DBG_VALUE $noreg, $noreg, %DW_AT_LLVM_lane_pc, DIExpression[ DW_OP_call_ref %__divergent_lane_pc_1_then; DW_OP_call_ref %__active_lane_pc; ]; b; %3 = EXEC; DBG_VALUE %3, %__lex_1_1_save_exec; %4 = c2; $lex_1_1_start: EXEC = %3 & %4; $lex_1_1_then: DEFINE_DWARF %__divergent_lane_pc_1_1_then = DW_TAG_dwarf_procedure[ DW_AT_name = "__divergent_lane_pc_1_1_then"; DW_AT_location = DIExpression[ DW_OP_call_ref %__divergent_lane_pc_1_then; DW_OP_addrx &lex_1_1_start; DW_OP_stack_value; DW_OP_LLVM_extend 64, 64; DW_OP_call_ref %__lex_1_1_save_exec; DW_OP_deref_type 64, %__uint_64; DW_OP_LLVM_select_bit_piece 64, 64; ]; ]; DBG_VALUE $noreg, $noreg, %DW_AT_LLVM_lane_pc, DIExpression[ DW_OP_call_ref %__divergent_lane_pc_1_1_then; DW_OP_call_ref %__active_lane_pc; ]; c; EXEC = ~EXEC & %3; $lex_1_1_else: DEFINE_DWARF %__divergent_lane_pc_1_1_else = DW_TAG_dwarf_procedure[ DW_AT_name = "__divergent_lane_pc_1_1_else"; DW_AT_location = DIExpression[ DW_OP_call_ref %__divergent_lane_pc_1_then; DW_OP_addrx &lex_1_1_end; DW_OP_stack_value; DW_OP_LLVM_extend 64, 64; DW_OP_call_ref %__lex_1_1_save_exec; DW_OP_deref_type 64, %__uint_64; DW_OP_LLVM_select_bit_piece 64, 64; ]; ]; DBG_VALUE $noreg, $noreg, %DW_AT_LLVM_lane_pc, DIExpression[ DW_OP_call_ref %__divergent_lane_pc_1_1_else; DW_OP_call_ref %__active_lane_pc; ]; d; EXEC = %3; $lex_1_1_end: DBG_VALUE $noreg, $noreg, %DW_AT_LLVM_lane_pc, DIExpression[ DW_OP_call_ref %__divergent_lane_pc; DW_OP_call_ref %__active_lane_pc; ]; e; EXEC = ~EXEC & %1; $lex_1_else: DEFINE_DWARF %__divergent_lane_pc_1_else = DW_TAG_dwarf_procedure[ DW_AT_name = "__divergent_lane_pc_1_else"; DW_AT_location = DIExpression[ DW_OP_call_ref %__divergent_lane_pc; DW_OP_addrx &lex_1_end; DW_OP_stack_value; DW_OP_LLVM_extend 64, 64; DW_OP_call_ref %__lex_1_save_exec; DW_OP_deref_type 64, %__uint_64; DW_OP_LLVM_select_bit_piece 64, 64; ]; ]; DBG_VALUE $noreg, $noreg, %DW_AT_LLVM_lane_pc, DIExpression[ DW_OP_call_ref %__divergent_lane_pc_1_else; DW_OP_call_ref %__active_lane_pc; ]; f; EXEC = %1; $lex_1_end: DBG_VALUE $noreg, $noreg, %DW_AT_LLVM_lane_pc DIExpression[ DW_OP_call_ref %__divergent_lane_pc; DW_OP_call_ref %__active_lane_pc; ]; g; $lex_end:
The DWARF procedure %__active_lane_pc is used to update the lane pc elements that are active, with the current program location.
Artificial variables %__lex_1_save_exec and %__lex_1_1_save_exec are created for the execution masks saved on entry to a region. Using the DBG_VALUE pseudo instruction, location list entries will be created that describe where the artificial variables are allocated at any given program location. The compiler may allocate them to registers or spill them to memory.
The DWARF procedures for each region use the values of the saved execution mask artificial variables to only update the lanes that are active on entry to the region. All other lanes retain the value of the enclosing region where they were last active. If they were not active on entry to the subprogram, then will have the undefined location description.
Other structured control flow regions can be handled similarly. For example, loops would set the divergent program location for the region at the end of the loop. Any lanes active will be in the loop, and any lanes not active must have exited the loop.
An IF/THEN/ELSEIF/ELSEIF/... region can be treated as a nest of IF/THEN/ELSE regions.
The DWARF procedures can use the active lane artificial variable described in {ref}amdgpu-dwarf-amdgpu-dw-at-llvm-active-lane rather than the actual EXEC mask in order to support whole or quad wavefront mode.
(amdgpu-dwarf-amdgpu-dw-at-llvm-active-lane)=
DW_AT_LLVM_active_laneThe DW_AT_LLVM_active_lane attribute on a subprogram debugger information entry is used to specify the lanes that are conceptually active for a SIMT thread.
The execution mask may be modified to implement whole or quad wavefront mode operations. For example, all lanes may need to temporarily be made active to execute a whole wavefront operation. Such regions would save the EXEC mask, update it to enable the necessary lanes, perform the operations, and then restore the EXEC mask from the saved value. While executing the whole wavefront region, the conceptual execution mask is the saved value, not the EXEC value.
This is handled by defining an artificial variable for the active lane mask. The active lane mask artificial variable would be the actual EXEC mask for normal regions, and the saved execution mask for regions where the mask is temporarily updated. The location list expression created for this artificial variable is used to define the value of the DW_AT_LLVM_active_lane attribute.
DW_AT_LLVM_augmentationFor AMDGPU, the DW_AT_LLVM_augmentation attribute of a compilation unit debugger information entry has the following value for the augmentation string:
[amdgpu:v0.0]
The “vX.Y” specifies the major X and minor Y version number of the AMDGPU extensions used in the DWARF of the compilation unit. The version number conforms to [{ref}SEMVER <semver>].
DWARF Call Frame Information (CFI) describes how a consumer can virtually unwind call frames in a running process or core dump. See DWARF Version 5 section 6.4 and {ref}amdgpu-dwarf-call-frame-information.
For AMDGPU, the Common Information Entry (CIE) fields have the following values:
augmentation string contains the following null-terminated UTF-8 string:
[amd:v0.0]
The vX.Y specifies the major X and minor Y version number of the AMDGPU extensions used in this CIE or to the FDEs that use it. The version number conforms to [{ref}SEMVER <semver>].
address_size for the Global address space is defined in {ref}amdgpu-dwarf-address-space-identifier.
segment_selector_size is 0 as AMDGPU does not use a segment selector.
code_alignment_factor is 4 bytes.
:::{todo} Add to {ref}amdgpu-processor-table table. :::
data_alignment_factor is 4 bytes.
:::{todo} Add to {ref}amdgpu-processor-table table. :::
return_address_register is PC_32 for 32-bit processes and PC_64 for 64-bit processes defined in {ref}amdgpu-dwarf-register-identifier.
initial_instructions Since a subprogram X with fewer registers can be called from subprogram Y that has more allocated, X will not change any of the extra registers as it cannot access them. Therefore, the default rule for all columns is same value.
For AMDGPU the register number follows the numbering defined in {ref}amdgpu-dwarf-register-identifier.
For AMDGPU the instructions are variable size. A consumer can subtract 1 from the return address to get the address of a byte within the call site instructions. See DWARF Version 5 section 6.4.4.
See DWARF Version 5 section 6.1.
See DWARF Version 5 section 6.1.1.4.1 and {ref}amdgpu-dwarf-lookup-by-name.
For AMDGPU the lookup by name section header table:
augmentation_string_size (uword)
Set to the length of the
augmentation_stringvalue which is always a multiple of 4.
augmentation_string (sequence of UTF-8 characters)
Contains the following UTF-8 string null padded to a multiple of 4 bytes:
[amdgpu:v0.0]The “vX.Y” specifies the major X and minor Y version number of the AMDGPU extensions used in the DWARF of this index. The version number conforms to [{ref}
SEMVER <semver>].:::{note} This is different to the DWARF Version 5 definition that requires the first 4 characters to be the vendor ID. But this is consistent with the other augmentation strings and does allow multiple vendor contributions. However, backwards compatibility may be more desirable. :::
See DWARF Version 5 section 6.1.2.
For AMDGPU the lookup by address section header table:
address_size (ubyte)
Match the address size for the
Globaladdress space defined in {ref}amdgpu-dwarf-address-space-identifier.
segment_selector_size (ubyte)
AMDGPU does not use a segment selector so this is 0. The entries in the
.debug_arangesdo not have a segment selector.
See DWARF Version 5 section 6.2 and {ref}amdgpu-dwarf-line-number-information.
AMDGPU does not use the isa state machine registers and always sets it to 0. The instruction set must be obtained from the ELF file header e_flags field in the EF_AMDGPU_MACH bit position (see {ref}ELF Header <amdgpu-elf-header>). See DWARF Version 5 section 6.2.2.
:::{todo} Should the isa state machine register be used to indicate if the code is in wavefront32 or wavefront64 mode? Or used to specify the architecture ISA? :::
For AMDGPU the line number program header fields have the following values (see DWARF Version 5 section 6.2.4):
address_size (ubyte)
: Matches the address size for the Global address space defined in {ref}amdgpu-dwarf-address-space-identifier.
segment_selector_size (ubyte)
: AMDGPU does not use a segment selector so this is 0.
minimum_instruction_length (ubyte)
: For GFX9-GFX11 this is 4.
maximum_operations_per_instruction (ubyte)
: For GFX9-GFX11 this is 1.
Source text for online-compiled programs (for example, those compiled by the OpenCL language runtime) may be embedded into the DWARF Version 5 line table. See DWARF Version 5 section 6.2.4.1 which is updated by DWARF Extensions For Heterogeneous Debugging section {ref}DW_LNCT_LLVM_source <amdgpu-dwarf-line-number-information-dw-lnct-llvm-source>.
The Clang option used to control source embedding in AMDGPU is defined in {ref}amdgpu-clang-debug-options-table.
:::{list-table} AMDGPU Clang Debug Options :name: amdgpu-clang-debug-options-table :header-rows: 1 :widths: auto
For example:
-gembed-source
: Enable the embedded source.
-gno-embed-source
: Disable the embedded source.
See DWARF Version 5 section 7.4 and {ref}amdgpu-dwarf-32-bit-and-64-bit-dwarf-formats.
For AMDGPU:
amdgcn target architecture only the 64-bit process address space is supported.For AMDGPU the following values apply for each of the unit headers described in DWARF Version 5 sections 7.5.1.1, 7.5.1.2, and 7.5.1.3:
address_size (ubyte)
: Matches the address size for the Global address space defined in {ref}amdgpu-dwarf-address-space-identifier.
(amdgpu-code-conventions)=
This section provides code conventions used for each supported target triple OS (see {ref}amdgpu-target-triples).
This section provides code conventions used when the target triple OS is amdhsa (see {ref}amdgpu-target-triples).
(amdgpu-amdhsa-code-object-metadata)=
The code object metadata specifies extensible metadata associated with the code objects executed on HSA [{ref}HSA <hsa>] compatible runtimes (see {ref}amdgpu-os). The encoding and semantics of this metadata depends on the code object version; see {ref}amdgpu-amdhsa-code-object-metadata-v2, {ref}amdgpu-amdhsa-code-object-metadata-v3, {ref}amdgpu-amdhsa-code-object-metadata-v4 and {ref}amdgpu-amdhsa-code-object-metadata-v5.
Code object metadata is specified in a note record (see {ref}amdgpu-note-records) and is required when the target triple OS is amdhsa (see {ref}amdgpu-target-triples). It must contain the minimum information necessary to support the HSA compatible runtime kernel queries. For example, the segment sizes needed in a dispatch packet. In addition, a high-level language runtime may require other information to be included. For example, the AMD OpenCL runtime records kernel argument information.
(amdgpu-amdhsa-code-object-metadata-v2)=
:::{warning} Code object V2 generation is no longer supported by this version of LLVM. :::
Code object V2 metadata is specified by the NT_AMD_HSA_METADATA note record (see {ref}amdgpu-note-records-v2).
The metadata is specified as a YAML formatted string (see [{ref}YAML <yaml>] and YAML I/O).
:::{todo} Is the string null terminated? It probably should not if YAML allows it to contain null characters, otherwise it should be. :::
The metadata is represented as a single YAML document comprised of the mapping defined in table {ref}amdgpu-amdhsa-code-object-metadata-map-v2-table and referenced tables.
For boolean values, the string values of false and true are used for false and true respectively.
Additional information can be added to the mappings. To avoid conflicts, any non-AMD key names should be prefixed by “vendor-name.”.
:::{list-table} AMDHSA Code Object V2 Metadata Map :name: amdgpu-amdhsa-code-object-metadata-map-v2-table :header-rows: 1 :widths: auto
“Printf”
sequence of strings
Each string is encoded information about a printf function call. The encoded information is organized as fields separated by colon (‘:’):
ID:N:S[0]:S[1]:...:S[N-1]:FormatString
where:
ID : A 32-bit integer as a unique id for each printf function call
N : A 32-bit integer equal to the number of arguments of printf function call minus 1
S[i] (where i = 0, 1, ... , N-1) : 32-bit integers for the size in bytes of the i-th FormatString argument of the printf function call
FormatString : The format string passed to the printf function call.
amdgpu-amdhsa-code-object-kernel-metadata-map-v2-table for the definition of the mapping. :::%
:::{list-table} AMDHSA Code Object V2 Kernel Metadata Map :name: amdgpu-amdhsa-code-object-kernel-metadata-map-v2-table :header-rows: 1 :widths: auto
“Language”
string
Source language of the kernel. Values include:
amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-v2-table for the mapping definition.amdgpu-amdhsa-code-object-kernel-argument-metadata-map-v2-table for the definition of the mapping.amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-v2-table for the mapping definition. :::%
:::{list-table} AMDHSA Code Object V2 Kernel Attribute Metadata Map :name: amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-v2-table :header-rows: 1 :widths: auto
“ReqdWorkGroupSize”
sequence of 3 integers
If not 0, 0, 0 then all values must be >=1 and the dispatch work-group size X, Y, Z must correspond to the specified values. Defaults to 0, 0, 0.
Corresponds to the OpenCL reqd_work_group_size attribute.
“WorkGroupSizeHint”
sequence of 3 integers
The dispatch work-group size X, Y, Z is likely to be the specified values.
Corresponds to the OpenCL work_group_size_hint attribute.
“VecTypeHint”
string
The name of a scalar or vector type.
Corresponds to the OpenCL vec_type_hint attribute.
%
:::{list-table} AMDHSA Code Object V2 Kernel Argument Metadata Map :name: amdgpu-amdhsa-code-object-kernel-argument-metadata-map-v2-table :header-rows: 1 :widths: auto
“ValueKind”
string
Required
Kernel argument kind that specifies how to set up the corresponding argument. Values include:
“ByValue” : The argument is copied directly into the kernarg.
“GlobalBuffer” : A global address space pointer to the buffer data is passed in the kernarg.
“DynamicSharedPointer” : A group address space pointer to dynamically allocated LDS is passed in the kernarg.
“Sampler” : A global address space pointer to a S# is passed in the kernarg.
“Image” : A global address space pointer to a T# is passed in the kernarg.
“Pipe” : A global address space pointer to an OpenCL pipe is passed in the kernarg.
“Queue” : A global address space pointer to an OpenCL device enqueue queue is passed in the kernarg.
“HiddenGlobalOffsetX” : The OpenCL grid dispatch global offset for the X dimension is passed in the kernarg.
“HiddenGlobalOffsetY” : The OpenCL grid dispatch global offset for the Y dimension is passed in the kernarg.
“HiddenGlobalOffsetZ” : The OpenCL grid dispatch global offset for the Z dimension is passed in the kernarg.
“HiddenNone” : An argument that is not used by the kernel. Space needs to be left for it, but it does not need to be set up.
“HiddenPrintfBuffer” : A global address space pointer to the runtime printf buffer is passed in kernarg. Mutually exclusive with “HiddenHostcallBuffer”.
“HiddenHostcallBuffer” : A global address space pointer to the runtime hostcall buffer is passed in kernarg. Mutually exclusive with “HiddenPrintfBuffer”.
“HiddenDefaultQueue” : A global address space pointer to the OpenCL device enqueue queue that should be used by the kernel by default is passed in the kernarg.
“HiddenCompletionAction” : A global address space pointer to help link enqueued kernels into the ancestor tree for determining when the parent kernel has finished.
“HiddenMultiGridSyncArg” : A global address space pointer for multi-grid synchronization is passed in the kernarg.
“AddrSpaceQual”
string
Kernel argument address space qualifier. Only present if “ValueKind” is “GlobalBuffer” or “DynamicSharedPointer”. Values are:
Is GlobalBuffer only Global or Constant? Is DynamicSharedPointer always Local? Can HCC allow Generic? How can Private or Region ever happen?
“AccQual”
string
Kernel argument access qualifier. Only present if “ValueKind” is “Image” or “Pipe”. Values are:
Does this apply to GlobalBuffer?
“ActualAccQual”
string
The actual memory accesses performed by the kernel on the kernel argument. Only present if “ValueKind” is “GlobalBuffer”, “Image”, or “Pipe”. This may be more restrictive than indicated by “AccQual” to reflect what the kernel actually does. If not present then the runtime must assume what is implied by “AccQual” and “IsConst”. Values are:
“IsPipe”
boolean
Indicates if the kernel argument is pipe qualified. Only present if “ValueKind” is “Pipe”.
Can GlobalBuffer be pipe qualified?
:::
%
:::{list-table} AMDHSA Code Object V2 Kernel Code Properties Metadata Map :name: amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-v2-table :header-rows: 1 :widths: auto
(amdgpu-amdhsa-code-object-metadata-v3)=
:::{warning} Code object V3 generation is no longer supported by this version of LLVM. :::
Code object V3 and above metadata is specified by the NT_AMDGPU_METADATA note record (see {ref}amdgpu-note-records-v3-onwards).
The metadata is represented as Message Pack formatted binary data (see [{ref}MsgPack <msgpack>]). The top level is a Message Pack map that includes the keys defined in table {ref}amdgpu-amdhsa-code-object-metadata-map-table-v3 and referenced tables.
Additional information can be added to the maps. To avoid conflicts, any key names should be prefixed by “vendor-name.” where vendor-name can be the name of the vendor and specific vendor tool that generates the information. The prefix is abbreviated to simply “.” when it appears within a map that has been added by the same vendor-name.
:::{list-table} AMDHSA Code Object V3 Metadata Map :name: amdgpu-amdhsa-code-object-metadata-map-table-v3 :header-rows: 1 :widths: auto
“amdhsa.printf”
sequence of strings
Each string is encoded information about a printf function call. The encoded information is organized as fields separated by colon (‘:’):
ID:N:S[0]:S[1]:...:S[N-1]:FormatString
where:
ID : A 32-bit integer as a unique id for each printf function call
N : A 32-bit integer equal to the number of arguments of printf function call minus 1
S[i] (where i = 0, 1, ... , N-1) : 32-bit integers for the size in bytes of the i-th FormatString argument of the printf function call
FormatString : The format string passed to the printf function call.
amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3 for the definition of the keys included in that map. :::%
:::{list-table} AMDHSA Code Object V3 Kernel Metadata Map :name: amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3 :header-rows: 1 :widths: auto
“.language”
string
Source language of the kernel. Values include:
amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3 for the definition of the keys included in that map.“.reqd_workgroup_size”
sequence of 3 integers
If not 0, 0, 0 then all values must be >=1 and the dispatch work-group size X, Y, Z must correspond to the specified values. Defaults to 0, 0, 0.
Corresponds to the OpenCL reqd_work_group_size attribute.
“.workgroup_size_hint”
sequence of 3 integers
The dispatch work-group size X, Y, Z is likely to be the specified values.
Corresponds to the OpenCL work_group_size_hint attribute.
“.vec_type_hint”
string
The name of a scalar or vector type.
Corresponds to the OpenCL vec_type_hint attribute.
“.kind”
string
The kind of the kernel with the following values:
“normal” : Regular kernels.
“init” : These kernels must be invoked after loading the containing code object and must complete before any normal and fini kernels in the same code object are invoked.
“fini” : These kernels must be invoked before unloading the containing code object and after all init and normal kernels in the same code object have been invoked and completed.
If omitted, “normal” is assumed.
%
:::{list-table} AMDHSA Code Object V3 Kernel Argument Metadata Map :name: amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3 :header-rows: 1 :widths: auto
“.value_kind”
string
Required
Kernel argument kind that specifies how to set up the corresponding argument. Values include:
“by_value” : The argument is copied directly into the kernarg.
“global_buffer” : A global address space pointer to the buffer data is passed in the kernarg.
“dynamic_shared_pointer” : A group address space pointer to dynamically allocated LDS is passed in the kernarg.
“sampler” : A global address space pointer to a S# is passed in the kernarg.
“image” : A global address space pointer to a T# is passed in the kernarg.
“pipe” : A global address space pointer to an OpenCL pipe is passed in the kernarg.
“queue” : A global address space pointer to an OpenCL device enqueue queue is passed in the kernarg.
“hidden_global_offset_x” : The OpenCL grid dispatch global offset for the X dimension is passed in the kernarg.
“hidden_global_offset_y” : The OpenCL grid dispatch global offset for the Y dimension is passed in the kernarg.
“hidden_global_offset_z” : The OpenCL grid dispatch global offset for the Z dimension is passed in the kernarg.
“hidden_none” : An argument that is not used by the kernel. Space needs to be left for it, but it does not need to be set up.
“hidden_printf_buffer” : A global address space pointer to the runtime printf buffer is passed in kernarg. Mutually exclusive with “hidden_hostcall_buffer” before Code Object V5.
“hidden_hostcall_buffer” : A global address space pointer to the runtime hostcall buffer is passed in kernarg. Mutually exclusive with “hidden_printf_buffer” before Code Object V5.
“hidden_default_queue” : A global address space pointer to the OpenCL device enqueue queue that should be used by the kernel by default is passed in the kernarg.
“hidden_completion_action” : A global address space pointer to help link enqueued kernels into the ancestor tree for determining when the parent kernel has finished.
“hidden_multigrid_sync_arg” : A global address space pointer for multi-grid synchronization is passed in the kernarg.
“.address_space”
string
Kernel argument address space qualifier. Only present if “.value_kind” is “global_buffer” or “dynamic_shared_pointer”. Values are:
Is "global_buffer" only "global" or "constant"? Is "dynamic_shared_pointer" always "local"? Can HCC allow "generic"? How can "private" or "region" ever happen?
“.access”
string
Kernel argument access qualifier. Only present if “.value_kind” is “image” or “pipe”. Values are:
Does this apply to "global_buffer"?
“.actual_access”
string
The actual memory accesses performed by the kernel on the kernel argument. Only present if “.value_kind” is “global_buffer”, “image”, or “pipe”. This may be more restrictive than indicated by “.access” to reflect what the kernel actually does. If not present then the runtime must assume what is implied by “.access” and “.is_const”. Values are:
“.is_pipe”
boolean
Indicates if the kernel argument is pipe qualified. Only present if “.value_kind” is “pipe”.
Can "global_buffer" be pipe qualified?
:::
(amdgpu-amdhsa-code-object-metadata-v4)=
:::{warning} Code object V4 is not the default code object version emitted by this version of LLVM. :::
Code object V4 metadata is the same as {ref}amdgpu-amdhsa-code-object-metadata-v3 with the changes and additions defined in table {ref}amdgpu-amdhsa-code-object-metadata-map-table-v4.
:::{list-table} AMDHSA Code Object V4 Metadata Map Changes :name: amdgpu-amdhsa-code-object-metadata-map-table-v4 :header-rows: 1 :widths: auto
“amdhsa.target”
string
Required
The target name of the code using the syntax:
<target-triple> [ "-" <target-id> ]
A canonical target ID must be used. See {ref}amdgpu-target-triples and {ref}amdgpu-target-id. :::
(amdgpu-amdhsa-code-object-metadata-v5)=
Code object V5 metadata is the same as {ref}amdgpu-amdhsa-code-object-metadata-v4 with the changes defined in table {ref}amdgpu-amdhsa-code-object-metadata-map-table-v5, table {ref}amdgpu-amdhsa-code-object-kernel-metadata-map-table-v5 and table {ref}amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v5.
:::{list-table} AMDHSA Code Object V5 Metadata Map Changes :name: amdgpu-amdhsa-code-object-metadata-map-table-v5 :header-rows: 1 :widths: auto
%
:::{list-table} AMDHSA Code Object V5 Kernel Metadata Map Additions :name: amdgpu-amdhsa-code-object-kernel-metadata-map-table-v5 :header-rows: 1 :widths: auto
amdgpu-amdhsa-kernel-descriptor-v3-table. :::%
:::{list-table} AMDHSA Code Object V5 Kernel Attribute Metadata Map :name: amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-v5-table :header-rows: 1 :widths: auto
%
%
:::{list-table} AMDHSA Code Object V5 Kernel Argument Metadata Map Additions and Changes :name: amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v5 :header-rows: 1 :widths: auto
“.value_kind”
string
Required
Kernel argument kind that specifies how to set up the corresponding argument. Values include: the same as code object V3 metadata (see {ref}amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3) with the following additions:
“hidden_block_count_x” : The grid dispatch work-group count for the X dimension is passed in the kernarg. Some languages, such as OpenCL, support a last work-group in each dimension being partial. This count only includes the non-partial work-group count. This is not the same as the value in the AQL dispatch packet, which has the grid size in work-items.
“hidden_block_count_y” : The grid dispatch work-group count for the Y dimension is passed in the kernarg. Some languages, such as OpenCL, support a last work-group in each dimension being partial. This count only includes the non-partial work-group count. This is not the same as the value in the AQL dispatch packet, which has the grid size in work-items. If the grid dimensionality is 1, then must be 1.
“hidden_block_count_z” : The grid dispatch work-group count for the Z dimension is passed in the kernarg. Some languages, such as OpenCL, support a last work-group in each dimension being partial. This count only includes the non-partial work-group count. This is not the same as the value in the AQL dispatch packet, which has the grid size in work-items. If the grid dimensionality is 1 or 2, then must be 1.
“hidden_group_size_x” : The grid dispatch work-group size for the X dimension is passed in the kernarg. This size only applies to the non-partial work-groups. This is the same value as the AQL dispatch packet work-group size.
“hidden_group_size_y” : The grid dispatch work-group size for the Y dimension is passed in the kernarg. This size only applies to the non-partial work-groups. This is the same value as the AQL dispatch packet work-group size. If the grid dimensionality is 1, then must be 1.
“hidden_group_size_z” : The grid dispatch work-group size for the Z dimension is passed in the kernarg. This size only applies to the non-partial work-groups. This is the same value as the AQL dispatch packet work-group size. If the grid dimensionality is 1 or 2, then must be 1.
“hidden_remainder_x” : The grid dispatch work group size of the partial work group of the X dimension, if it exists. Must be zero if a partial work group does not exist in the X dimension.
“hidden_remainder_y” : The grid dispatch work group size of the partial work group of the Y dimension, if it exists. Must be zero if a partial work group does not exist in the Y dimension.
“hidden_remainder_z” : The grid dispatch work group size of the partial work group of the Z dimension, if it exists. Must be zero if a partial work group does not exist in the Z dimension.
“hidden_grid_dims” : The grid dispatch dimensionality. This is the same value as the AQL dispatch packet dimensionality. Must be a value between 1 and 3.
“hidden_heap_v1” : A global address space pointer to an initialized memory buffer that conforms to the requirements of the malloc/free device library V1 version implementation.
“hidden_dynamic_lds_size” : Size of the dynamically allocated LDS memory is passed in the kernarg.
“hidden_private_base” : The high 32 bits of the flat addressing private aperture base. Only used by GFX8 to allow conversion between private segment and flat addresses. See {ref}amdgpu-amdhsa-kernel-prolog-flat-scratch.
“hidden_shared_base” : The high 32 bits of the flat addressing shared aperture base. Only used by GFX8 to allow conversion between shared segment and flat addresses. See {ref}amdgpu-amdhsa-kernel-prolog-flat-scratch.
“hidden_queue_ptr” : A global memory address space pointer to the ROCm runtime struct amd_queue_t structure for the HSA queue of the associated dispatch AQL packet. It is only required for pre-GFX9 devices for the trap handler ABI (see {ref}amdgpu-amdhsa-trap-handler-abi). :::
(amdgpu-amdhsa-code-object-metadata-v6)=
Code object V6 metadata is the same as {ref}amdgpu-amdhsa-code-object-metadata-v5 with the changes defined in table {ref}amdgpu-amdhsa-code-object-kernel-metadata-map-table-v6.
:::{list-table} AMDHSA Code Object V6 Kernel Metadata Map Additions :name: amdgpu-amdhsa-code-object-kernel-metadata-map-table-v6 :header-rows: 1 :widths: auto
The HSA architected queuing language (AQL) defines a user space memory interface that can be used to control the dispatch of kernels, in an agent independent way. An agent can have zero or more AQL queues created for it using an HSA compatible runtime (see {ref}amdgpu-os), in which AQL packets (all of which are 64 bytes) can be placed. See the HSA Platform System Architecture Specification [{ref}HSA <hsa>] for the AQL queue mechanics and packet layouts.
The packet processor of a kernel agent is responsible for detecting and dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the packet processor is implemented by the hardware command processor (CP), asynchronous dispatch controller (ADC) and shader processor input controller (SPI).
An HSA compatible runtime can be used to allocate an AQL queue object. It uses the kernel mode driver to initialize and register the AQL queue with CP.
To dispatch a kernel the following actions are performed. This can occur in the CPU host program, or from an HSA kernel executing on a GPU.
amdgpu-amdhsa-kernel-descriptor) of the kernel to execute is obtained. It must be for a kernel that is contained in a code object that was loaded by an HSA compatible runtime on the kernel agent with which the AQL queue is associated.HSA <hsa>]. For AMDGPU the kernel execution directly accesses the kernel argument memory in the same way constant memory is accessed. (Note that the HSA specification allows an implementation to copy the kernel argument contents to another location that is accessed by the kernel.)HSA <hsa>].amdgpu-amdhsa-code-object-metadata.amdgpu-amdhsa-kernel-descriptor. The initial register state is defined in {ref}amdgpu-amdhsa-initial-kernel-execution-state.amdgpu-amdhsa-kernel-prolog) sets up the machine state as necessary before continuing executing the machine code that corresponds to the kernel.(amdgpu-amdhsa-memory-spaces)=
The memory space properties are:
:::{list-table} AMDHSA Memory Spaces :name: amdgpu-amdhsa-memory-spaces-table :header-rows: 1 :widths: auto
The global and constant memory spaces both use global virtual addresses, which are the same virtual address space used by the CPU. However, some virtual addresses may only be accessible to the CPU, some only accessible by the GPU, and some by both.
Using the constant memory space indicates that the data will not change during the execution of the kernel. This allows scalar read instructions to be used. The vector and scalar L1 caches are invalidated of volatile data before each kernel dispatch execution to allow constant memory to change values between kernel dispatches.
The local memory space uses the hardware Local Data Store (LDS) which is automatically allocated when the hardware creates work-groups of wavefronts, and freed when all the wavefronts of a work-group have terminated. The data store (DS) instructions can be used to access it.
The private memory space uses the hardware scratch memory support. If the kernel uses scratch, then the hardware allocates memory that is accessed using wavefront lane dword (4 byte) interleaving. The mapping used from private address to physical address is:
wavefront-scratch-base + (private-address * wavefront-size * 4) + (wavefront-lane-id * 4)
There are different ways that the wavefront scratch base address is determined by a wavefront (see {ref}amdgpu-amdhsa-initial-kernel-execution-state). This memory can be accessed in an interleaved manner using buffer instruction with the scratch buffer descriptor and per wavefront scratch offset, by the scratch instructions, or by flat instructions. If each lane of a wavefront accesses the same private address, the interleaving results in adjacent dwords being accessed and hence requires fewer cache lines to be fetched. Multi-dword access is not supported except by flat and scratch instructions in GFX9-GFX11.
The generic address space uses the hardware flat address support available in GFX7-GFX11. This uses two fixed ranges of virtual addresses (the private and local apertures), that are outside the range of addressable global memory, to map from a flat address to a private or local address.
FLAT instructions can take a flat address and access global, private (scratch) and group (LDS) memory depending on if the address is within one of the aperture ranges. Flat access to scratch requires hardware aperture setup and setup in the kernel prologue (see {ref}amdgpu-amdhsa-kernel-prolog-flat-scratch). Flat access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup (see {ref}amdgpu-amdhsa-kernel-prolog-m0).
To convert between a segment address and a flat address the base address of the apertures address can be used. For GFX7-GFX8 these are available in the {ref}amdgpu-amdhsa-hsa-aql-queue the address of which can be obtained with Queue Ptr SGPR (see {ref}amdgpu-amdhsa-initial-kernel-execution-state). For GFX9-GFX11 the aperture base addresses are directly available as inline constant registers SRC_SHARED_BASE/LIMIT and SRC_PRIVATE_BASE/LIMIT. In 64-bit address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32 which makes it easier to convert from flat to segment or segment to flat.
Image and sample handles created by an HSA compatible runtime (see {ref}amdgpu-os) are 64-bit addresses of a hardware 32-byte V# and 48 byte S# object respectively. In order to support the HSA query_sampler operations two extra dwords are used to store the HSA BRIG enumeration values for the queries that are not trivially deducible from the S# representation.
HSA signal handles created by an HSA compatible runtime (see {ref}amdgpu-os) are 64-bit addresses of a structure allocated in memory accessible from both the CPU and GPU. The structure is defined by the runtime and subject to change between releases. For example, see [{ref}AMD-ROCm-github <amd-rocm-github>].
(amdgpu-amdhsa-hsa-aql-queue)=
The HSA AQL queue structure is defined by an HSA compatible runtime (see {ref}amdgpu-os) and subject to change between releases. For example, see [{ref}AMD-ROCm-github <amd-rocm-github>]. For some processors it contains fields needed to implement certain language features such as the flat address aperture bases. It also contains fields used by CP such as managing the allocation of scratch memory.
(amdgpu-amdhsa-kernel-descriptor)=
A kernel descriptor consists of the information needed by CP to initiate the execution of a kernel, including the entry point address of the machine code that implements the kernel.
CP microcode requires the Kernel descriptor to be allocated on 64-byte alignment.
The fields used by CP for code objects before V3 also match those specified in {ref}amdgpu-amdhsa-kernel-descriptor-v3-table.
:::{list-table} Code Object V3 Kernel Descriptor :name: amdgpu-amdhsa-kernel-descriptor-v3-table :header-rows: 1 :widths: auto
95:64
4 bytes
KERNARG_SIZE
The size of the kernarg memory pointed to by the AQL dispatch packet. The kernarg memory is used to pass arguments to the kernel.
383:352
4 bytes
COMPUTE_PGM_RSRC3
GFX6-GFX9 : Reserved, must be 0.
GFX90A, GFX942 : Compute Shader (CS) program settings used by CP to set up COMPUTE_PGM_RSRC3 configuration register. See {ref}amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table.
GFX10-GFX11 : Compute Shader (CS) program settings used by CP to set up COMPUTE_PGM_RSRC3 configuration register. See {ref}amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table.
GFX12 : Compute Shader (CS) program settings used by CP to set up COMPUTE_PGM_RSRC3 configuration register. See {ref}amdgpu-amdhsa-compute_pgm_rsrc3-gfx12-table.
COMPUTE_PGM_RSRC1 configuration register. See {ref}amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table.COMPUTE_PGM_RSRC2 configuration register. See {ref}amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table.458:448
7 bits
See separate bits below.
Enable the setup of the SGPR user data registers (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).
The total number of SGPR user data registers requested must not exceed 16 and match value in compute_pgm_rsrc2.user_sgpr.user_sgpr_count. Any requests beyond 16 will be ignored.
amdgpu-processor-table specifies Architected flat scratch then not supported and must be 0,amdgpu-processor-table specifies Architected flat scratch then not supported and must be 0,458
1 bit
ENABLE_WAVEFRONT_SIZE32
GFX6-GFX9 : Reserved, must be 0.
GFX10-GFX11 : - If 0 execute in wavefront size 64 mode.
470:464
7 bits
KERNARG_PRELOAD_SPEC_LENGTH
GFX6-GFX9 : - Reserved, must be 0.
GFX90A, GFX942 : - The number of dwords from the kernarg segment to preload into User SGPRs before kernel execution. (see {ref}amdgpu-amdhsa-kernarg-preload).
479:471
9 bits
KERNARG_PRELOAD_SPEC_OFFSET
GFX6-GFX9 : - Reserved, must be 0.
GFX90A, GFX942 : - An offset in dwords into the kernarg segment to begin preloading data into User SGPRs. (see {ref}amdgpu-amdhsa-kernarg-preload).
:::
%
:::{list-table} compute_pgm_rsrc1 for GFX6-GFX12 :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table :header-rows: 1 :widths: auto
5:0
6 bits
GRANULATED_WORKITEM_VGPR_COUNT
Number of vector register blocks used by each work-item; granularity is device specific:
GFX6-GFX9 : - vgprs_used 0..256
GFX90A, GFX942 : - vgprs_used 0..512
GFX10-GFX12 (wavefront size 64) : - max_vgpr 1..256
GFX10-GFX12 (wavefront size 32) : - max_vgpr 1..256
GFX125X (wavefront size 32) : - max_vgpr 1..1024
Where vgprs_used is defined as the highest VGPR number explicitly referenced plus one.
Used by CP to set up COMPUTE_PGM_RSRC1.VGPRS.
The {ref}amdgpu-assembler calculates this automatically for the selected processor from values provided to the .amdhsa_kernel directive by the .amdhsa_next_free_vgpr nested directive (see {ref}amdhsa-kernel-directives-table).
9:6
4 bits
GRANULATED_WAVEFRONT_SGPR_COUNT
Number of scalar register blocks used by a wavefront; granularity is device specific:
GFX6-GFX8 : - sgprs_used 0..112
GFX9 : - sgprs_used 0..112
GFX10-GFX12 : Reserved, must be 0. (128 SGPRs always allocated.)
Where sgprs_used is defined as the highest SGPR number explicitly referenced plus one, plus a target specific number of additional special SGPRs for VCC, FLAT_SCRATCH (GFX7+) and XNACK_MASK (GFX8+), and any additional target specific limitations. It does not include the 16 SGPRs added if a trap handler is enabled.
The target specific limitations and special SGPR layout are defined in the hardware documentation, which can be found in the {ref}amdgpu-processors table.
Used by CP to set up COMPUTE_PGM_RSRC1.SGPRS.
The {ref}amdgpu-assembler calculates this automatically for the selected processor from values provided to the .amdhsa_kernel directive by the .amdhsa_next_free_sgpr and .amdhsa_reserve_* nested directives (see {ref}amdhsa-kernel-directives-table).
11:10
2 bits
PRIORITY
Must be 0.
Start executing wavefront at the specified priority.
CP is responsible for filling in COMPUTE_PGM_RSRC1.PRIORITY.
13:12
2 bits
FLOAT_ROUND_MODE_32
Wavefront starts execution with specified rounding mode for single (32-bit) floating point precision floating point operations.
Floating point rounding mode values are defined in {ref}amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table.
Used by CP to set up COMPUTE_PGM_RSRC1.FLOAT_MODE.
15:14
2 bits
FLOAT_ROUND_MODE_16_64
Wavefront starts execution with specified rounding denorm mode for half/double (16 and 64-bit) floating point precision floating point operations.
Floating point rounding mode values are defined in {ref}amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table.
Used by CP to set up COMPUTE_PGM_RSRC1.FLOAT_MODE.
17:16
2 bits
FLOAT_DENORM_MODE_32
Wavefront starts execution with specified denorm mode for single (32 bit) floating point precision floating point operations.
Floating point denorm mode values are defined in {ref}amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table.
Used by CP to set up COMPUTE_PGM_RSRC1.FLOAT_MODE.
19:18
2 bits
FLOAT_DENORM_MODE_16_64
Wavefront starts execution with specified denorm mode for half/double (16 and 64-bit) floating point precision floating point operations.
Floating point denorm mode values are defined in {ref}amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table.
Used by CP to set up COMPUTE_PGM_RSRC1.FLOAT_MODE.
20
1 bit
PRIV
Must be 0.
Start executing wavefront in privilege trap handler mode.
CP is responsible for filling in COMPUTE_PGM_RSRC1.PRIV.
21
1 bit
ENABLE_DX10_CLAMP
WG_RR_EN
GFX9-GFX11 (except GFX11.7) : Wavefront starts execution with DX10 clamp mode enabled. Used by the vector ALU to force DX10 style treatment of NaN's (when set, clamp NaN to zero, otherwise pass NaN through).
Used by CP to set up COMPUTE_PGM_RSRC1.DX10_CLAMP.
GFX11.7 : Reserved. Must be 0.
GFX12 : If 1, wavefronts are scheduled in a round-robin fashion with respect to the other wavefronts of the SIMD. Otherwise, wavefronts are scheduled in oldest age order.
CP is responsible for filling in COMPUTE_PGM_RSRC1.WG_RR_EN.
22
1 bit
DEBUG_MODE
Must be 0.
Start executing wavefront in single step mode.
CP is responsible for filling in COMPUTE_PGM_RSRC1.DEBUG_MODE.
23
1 bit
ENABLE_IEEE_MODE
DISABLE_PERF
GFX9-GFX11 (except GFX11.7) : Wavefront starts execution with IEEE mode enabled. Floating point opcodes that support exception flag gathering will quiet and propagate signaling-NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10 become IEEE 754-2008 compliant due to signaling-NaN propagation and quieting.
Used by CP to set up COMPUTE_PGM_RSRC1.IEEE_MODE.
GFX11.7 : Reserved. Must be 0.
GFX12 : Reserved. Must be 0.
24
1 bit
BULKY
Must be 0.
Only one work-group allowed to execute on a compute unit.
CP is responsible for filling in COMPUTE_PGM_RSRC1.BULKY.
25
1 bit
CDBG_USER
Must be 0.
Flag that can be used to control debugging code.
CP is responsible for filling in COMPUTE_PGM_RSRC1.CDBG_USER.
26
1 bit
FP16_OVFL
GFX6-GFX8 : Reserved, must be 0.
GFX9-GFX12 : Wavefront starts execution with specified fp16 overflow mode.
Used by CP to set up COMPUTE_PGM_RSRC1.FP16_OVFL.
27
1 bit
RESERVED
FLAT_SCRATCH_IS_NV
GFX6-GFX120* : Reserved, must be 0.
GFX125* : 0 - Use the NV ISA as indication that scratch is NV. 1 - Force scratch to NV = 1, even if ISA.NV == 0 if the address falls into scratch space (not global). This allows global.NV = 0 and scratch.NV = 1 for flat ops. Other threads use the ISA bit value.
Used by CP to set up COMPUTE_PGM_RSRC1.FLAT_SCRATCH_IS_NV.
29
1 bit
WGP_MODE
GFX6-GFX9 : Reserved, must be 0.
GFX10-GFX12 : - If 0 execute work-groups in CU wavefront execution mode.
See {ref}amdgpu-amdhsa-memory-model.
Used by CP to set up COMPUTE_PGM_RSRC1.WGP_MODE.
30
1 bit
MEM_ORDERED
GFX6-GFX9 : Reserved, must be 0.
GFX10-GFX12 : Controls the behavior of the s_waitcnt's vmcnt and vscnt counters.
Used by CP to set up COMPUTE_PGM_RSRC1.MEM_ORDERED.
31
1 bit
FWD_PROGRESS
GFX6-GFX9 : Reserved, must be 0.
GFX10-GFX12 : - If 0 execute SIMD wavefronts using oldest first policy.
Used by CP to set up COMPUTE_PGM_RSRC1.FWD_PROGRESS.
:::
%
:::{list-table} compute_pgm_rsrc2 for GFX6-GFX12 :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table :header-rows: 1 :widths: auto
0
1 bit
ENABLE_PRIVATE_SEGMENT
amdgpu-processor-table does not specify Architected flat scratch then enable the setup of the SGPR wavefront scratch offset system register (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).amdgpu-processor-table specifies Architected flat scratch then enable the setup of the FLAT_SCRATCH register pair (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).Used by CP to set up COMPUTE_PGM_RSRC2.SCRATCH_EN.
5:1
5 bits
USER_SGPR_COUNT
GFX6-GFX120* : The total number of SGPR user data registers requested. This number must be greater than or equal to the number of user data registers enabled.
Used by CP to set up COMPUTE_PGM_RSRC2.USER_SGPR.
6
1 bit
ENABLE_TRAP_HANDLER
ENABLE_DYNAMIC_VGPR
GFX6-GFX11 : Must be 0.
This bit represents COMPUTE_PGM_RSRC2.TRAP_PRESENT, which is set by the CP if the runtime has installed a trap handler.
GFX120* : Enables dynamic VGPR mode, where each wave allocates one VGPR chunk at launch and can request for additional space to use during execution in SQ.
Used by CP to set up COMPUTE_PGM_RSRC2.DYNAMIC_VGPR.
6:1
6 bits
USER_SGPR_COUNT
GFX125* : The total number of SGPR user data registers requested. This number must be greater than or equal to the number of user data registers enabled.
Used by CP to set up COMPUTE_PGM_RSRC2.USER_SGPR.
7
1 bit
ENABLE_SGPR_WORKGROUP_ID_X
Enable the setup of the system SGPR register for the work-group id in the X dimension (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).
Used by CP to set up COMPUTE_PGM_RSRC2.TGID_X_EN.
8
1 bit
ENABLE_SGPR_WORKGROUP_ID_Y
Enable the setup of the system SGPR register for the work-group id in the Y dimension (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).
Used by CP to set up COMPUTE_PGM_RSRC2.TGID_Y_EN.
9
1 bit
ENABLE_SGPR_WORKGROUP_ID_Z
Enable the setup of the system SGPR register for the work-group id in the Z dimension (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).
Used by CP to set up COMPUTE_PGM_RSRC2.TGID_Z_EN.
10
1 bit
ENABLE_SGPR_WORKGROUP_INFO
Enable the setup of the system SGPR register for work-group information (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).
Used by CP to set up COMPUTE_PGM_RSRC2.TGID_SIZE_EN.
12:11
2 bits
ENABLE_VGPR_WORKITEM_ID
Enable the setup of the VGPR system registers used for the work-item ID. {ref}amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table defines the values.
Used by CP to set up COMPUTE_PGM_RSRC2.TIDIG_CMP_CNT.
13
1 bit
ENABLE_EXCEPTION_ADDRESS_WATCH
Must be 0.
Wavefront starts execution with address watch exceptions enabled which are generated when L1 has witnessed a thread access an address of interest.
CP is responsible for filling in the address watch bit in COMPUTE_PGM_RSRC2.EXCP_EN_MSB according to what the runtime requests.
14
1 bit
ENABLE_EXCEPTION_MEMORY
Must be 0.
Wavefront starts execution with memory violation exceptions enabled which are generated when a memory violation has occurred for this wavefront from L1 or LDS (write-to-read-only-memory, mis-aligned atomic, LDS address out of range, illegal address, etc.).
CP sets the memory violation bit in COMPUTE_PGM_RSRC2.EXCP_EN_MSB according to what the runtime requests.
23:15
9 bits
GRANULATED_LDS_SIZE
Must be 0.
CP uses the rounded value from the dispatch packet, not this value, as the dispatch may contain dynamically allocated group segment memory. CP writes directly to COMPUTE_PGM_RSRC2.LDS_SIZE.
Amount of group segment (LDS) to allocate for each work-group. Granularity is device specific:
GFX6 : roundup(lds-size / (64 * 4))
GFX7-GFX12 : roundup(lds-size / (128 * 4))
GFX950 : roundup(lds-size / (320 * 4))
GFX125* : roundup(lds-size / (512 * 4))
GFX13 : roundup(lds-size / (256 * 4))
24
1 bit
ENABLE_EXCEPTION_IEEE_754_FP _INVALID_OPERATION
Wavefront starts execution with specified exceptions enabled.
Used by CP to set up COMPUTE_PGM_RSRC2.EXCP_EN (set from bits 0..6).
IEEE 754 FP Invalid Operation
:::
%
:::{list-table} compute_pgm_rsrc3 for GFX90A, GFX942 :name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table :header-rows: 1 :widths: auto
:::
%
:::{list-table} compute_pgm_rsrc3 for GFX10-GFX11 :name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table :header-rows: 1 :widths: auto
9:4
6 bits
INST_PREF_SIZE
GFX10 : Reserved, must be 0.
GFX11 : Number of instruction bytes to prefetch, starting at the kernel's entry point instruction, before wavefront starts execution. The value is 0..63 with a granularity of 128 bytes.
10
1 bit
TRAP_ON_START
GFX10 : Reserved, must be 0.
GFX11 : Must be 0.
If 1, wavefront starts execution by trapping into the trap handler.
CP is responsible for filling in the trap on start bit in COMPUTE_PGM_RSRC3.TRAP_ON_START according to what the runtime requests.
11
1 bit
TRAP_ON_END
GFX10 : Reserved, must be 0.
GFX11 : Must be 0.
If 1, wavefront execution terminates by trapping into the trap handler.
CP is responsible for filling in the trap on end bit in COMPUTE_PGM_RSRC3.TRAP_ON_END according to what the runtime requests.
31
1 bit
IMAGE_OP
GFX10 : Reserved, must be 0.
GFX11 : If 1, the kernel execution contains image instructions. If executed as part of a graphics pipeline, image read instructions will stall waiting for any necessary WAIT_SYNC fence to be performed in order to indicate that earlier pipeline stages have completed writing to the image.
Not used for compute kernels that are not part of a graphics pipeline and must be 0.
:::
%
:::{list-table} compute_pgm_rsrc3 for GFX12 :name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx12-table :header-rows: 1 :widths: auto
16:14
3 bits
RESERVED
NAMED_BAR_CNT
GFX120* : Reserved, must be 0.
GFX125* : Number of named barriers to alloc for each workgroup, in granularity of 4. Range is from 0-4 allocating 0, 4, 8, 12, 16.
17
1 bit
RESERVED
ENABLE_DYNAMIC_VGPR
GFX120* : Reserved, must be 0.
GFX125* : Enables dynamic VGPR mode, where each wave allocates one VGPR chunk at launch and can request for additional space to use during execution in SQ.
Used by CP to set up COMPUTE_PGM_RSRC3.DYNAMIC_VGPR.
20:18
3 bits
RESERVED
TCP_SPLIT
GFX120* : Reserved, must be 0.
GFX125* : Desired LDS/VC split of TCP. 0: no preference 1: LDS=0, VC=448kB 2: LDS=64kB, VC=384kB 3: LDS=128kB, VC=320kB 4: LDS=192kB, VC=256kB 5: LDS=256kB, VC=192kB 6: LDS=320kB, VC=128kB 7: LDS=384kB, VC=64kB
21
1 bit
RESERVED
ENABLE_DIDT_THROTTLE
GFX120* : Reserved, must be 0.
GFX125* : Enable DIDT throttling for all ACE pipes
31
1 bit
IMAGE_OP
If 1, the kernel execution contains image instructions. If executed as part of a graphics pipeline, image read instructions will stall waiting for any necessary WAIT_SYNC fence to be performed in order to indicate that earlier pipeline stages have completed writing to the image.
Not used for compute kernels that are not part of a graphics pipeline and must be 0.
:::
%
:::{list-table} Floating Point Rounding Mode Enumeration Values :name: amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table :header-rows: 1 :widths: auto
:::{list-table} Extended FLT_ROUNDS Enumeration Values :name: amdgpu-rounding-mode-enumeration-values-table :widths: auto
%
:::{list-table} Floating Point Denorm Mode Enumeration Values :name: amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table :header-rows: 1 :widths: auto
Denormal flushing is sign respecting, i.e., the behavior expected by "denormal-fp-math"="preserve-sign". The behavior is undefined with "denormal-fp-math"="positive-zero"
%
:::{list-table} System VGPR Work-Item ID Enumeration Values :name: amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table :header-rows: 1 :widths: auto
(amdgpu-amdhsa-initial-kernel-execution-state)=
This section defines the register state that will be set up by the packet processor prior to the start of execution of every wavefront. This is limited by the constraints of the hardware controllers of CP/ADC/SPI.
The order of the SGPR registers is defined, but the compiler can specify which ones are actually setup in the kernel descriptor using the enable_sgpr_* bit fields (see {ref}amdgpu-amdhsa-kernel-descriptor). The register numbers used for enabled registers are dense starting at SGPR0: the first enabled register is SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have an SGPR number.
The initial SGPRs comprise up to 16 User SGPRs that are set by CP and apply to all wavefronts of the grid. It is possible to specify more than 16 User SGPRs using the enable_sgpr_* bit fields, in which case only the first 16 are actually initialized. These are then immediately followed by the System SGPRs that are set up by ADC/SPI and can have different values for each wavefront of the grid dispatch.
SGPR register initial state is defined in {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
:::{list-table} SGPR Register Set Up Order :name: amdgpu-amdhsa-sgpr-register-set-up-order-table :header-rows: 1 :widths: auto
amdgpu-amdhsa-kernel-prolog-private-segment-buffer.then
Kernarg Segment Ptr (enable_sgpr_kernarg _segment_ptr)
2
64-bit address of Kernarg segment. This is directly copied from the kernarg_address in the kernel dispatch packet.
Having CP load it once avoids loading it at the beginning of every wavefront.
amdgpu-amdhsa-kernel-prolog-flat-scratch.then
Private Segment Size (enable_sgpr_private _segment_size)
1
The 32-bit byte size of a single work-item's memory allocation. This is the value from the kernel dispatch packet Private Segment Byte Size rounded up by CP to a multiple of DWORD.
Having CP load it once avoids loading it at the beginning of every wavefront.
This is not used for GFX7-GFX8 since it is the same value as the second SGPR of Flat Scratch Init. However, it may be needed for GFX9-GFX11 which changes the meaning of the Flat Scratch Init value.
amdgpu-amdhsa-kernarg-preload.amdgpu-amdhsa-kernel-prolog-flat-scratch. and {ref}amdgpu-amdhsa-kernel-prolog-private-segment-buffer. :::The order of the VGPR registers is defined, but the compiler can specify which ones are actually setup in the kernel descriptor using the enable_vgpr* bit fields (see {ref}amdgpu-amdhsa-kernel-descriptor). The register numbers used for enabled registers are dense starting at VGPR0: the first enabled register is VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a VGPR number.
There are different methods used for the VGPR initial state:
Unless the Target Properties column of {ref}amdgpu-processor-table specifies otherwise, a separate VGPR register is used per work-item ID. The VGPR register initial state for this method is defined in {ref}amdgpu-amdhsa-vgpr-register-set-up-order-for-unpacked-work-item-id-method-table.
If Target Properties column of {ref}amdgpu-processor-table specifies Packed work-item IDs, the initial value of VGPR0 register is used for all work-item IDs. The register layout for this method is defined in {ref}amdgpu-amdhsa-register-layout-for-packed-work-item-id-method-table.
:::{list-table} VGPR Register Set Up Order for Unpacked Work-Item ID Method :name: amdgpu-amdhsa-vgpr-register-set-up-order-for-unpacked-work-item-id-method-table :header-rows: 1
%
:::{list-table} Register Layout for Packed Work-Item ID Method :name: amdgpu-amdhsa-register-layout-for-packed-work-item-id-method-table :header-rows: 1 :widths: auto
0:9
10 bits
Work-Item Id X
Work-item id in X dimension of work-group for wavefront lane.
Always initialized.
10:19
10 bits
Work-Item Id Y
Work-item id in Y dimension of work-group for wavefront lane.
Initialized if enable_vgpr_workitem_id > 0, otherwise set to 0.
20:29
10 bits
Work-Item Id Z
Work-item id in Z dimension of work-group for wavefront lane.
Initialized if enable_vgpr_workitem_id > 1, otherwise set to 0.
The setting of registers is done by GPU CP/ADC/SPI hardware as follows:
amdgpu-amdhsa-kernel-prolog-flat-scratch).amdgpu-amdhsa-kernel-prolog-flat-scratch.The global segment can be accessed either using buffer instructions (GFX6 which has V# 64-bit address support), flat instructions (GFX7-GFX11), or global instructions (GFX9-GFX11).
If buffer operations are used, then the compiler can generate a V# with the following properties:
(amdgpu-amdhsa-kernarg-preload)=
On hardware that supports this feature, kernel arguments can be preloaded into User SGPRs, up to the maximum number of User SGPRs available. The allocation of Preload SGPRs occurs directly after the last enabled non-kernarg preload User SGPR. (See {ref}amdgpu-amdhsa-initial-kernel-execution-state)
The data preloaded is copied from the kernarg segment, the amount of data is determined by the value specified in the kernarg_preload_spec_length field of the kernel descriptor. This data is then loaded into consecutive User SGPRs. The number of SGPRs receiving preloaded kernarg data corresponds with the value given by kernarg_preload_spec_length. The preloading starts at the dword offset within the kernarg segment, which is specified by the kernarg_preload_spec_offset field.
If the kernarg_preload_spec_length is non-zero, the CP firmware will append an additional 256 bytes to the kernel_code_entry_byte_offset. This addition facilitates the incorporation of a prologue to the kernel entry to handle cases where code designed for kernarg preloading is executed on hardware equipped with incompatible firmware. If hardware has compatible firmware the 256 bytes at the start of the kernel entry will be skipped.
With code object V5 and later, hidden kernel arguments that are normally accessed through the Implicit Argument Ptr, may be preloaded into User SGPRs. These arguments are added to the kernel function signature and are marked with the attributes “inreg” and “amdgpu-hidden-argument”. (See {ref}amdgpu-llvm-ir-attributes-table).
(amdgpu-amdhsa-kernel-prolog)=
The compiler performs initialization in the kernel prologue depending on the target and information about things like stack usage in the kernel and called functions. Some of this initialization requires the compiler to request certain User and System SGPRs be present in the {ref}amdgpu-amdhsa-initial-kernel-execution-state via the {ref}amdgpu-amdhsa-kernel-descriptor.
(amdgpu-amdhsa-kernel-prolog-cfi)=
DW_ASPACE_AMDGPU_private_wave address space address 0.(amdgpu-amdhsa-kernel-prolog-m0)=
GFX6-GFX8
: The M0 register must be initialized with a value at least the total LDS size if the kernel may access LDS via DS or flat operations. Total LDS size is available in dispatch packet. For M0, it is also possible to use maximum possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for GFX7-GFX8).
GFX9 and later
: The M0 register is not used for range checking LDS accesses and so does not need to be initialized in the prolog.
(amdgpu-amdhsa-kernel-prolog-stack-pointer)=
If the kernel has function calls it must set up the ABI stack pointer described in {ref}amdgpu-amdhsa-function-call-convention-non-kernel-functions by setting SGPR32 to the unswizzled scratch offset of the address past the last local allocation.
(amdgpu-amdhsa-kernel-prolog-frame-pointer)=
If the kernel needs a frame pointer for the reasons defined in SIFrameLowering then SGPR33 is used and is always set to 0 in the kernel prolog. On GFX12+, when dynamic VGPRs are enabled, the prologue will check if the kernel is running on a compute queue, and if so it will reserve some scratch space for any dynamic VGPRs that might need to be saved by the CWSR trap handler. In this case, the frame pointer will be initialized to a suitably aligned offset above this reserved area. If a frame pointer is not required then all uses of the frame pointer are replaced with immediate 0 offsets.
(amdgpu-amdhsa-kernel-prolog-flat-scratch)=
There are different methods used for initializing flat scratch:
If the Target Properties column of {ref}amdgpu-processor-table specifies Does not support generic address space:
Flat scratch is not supported and there is no flat scratch register pair.
If the Target Properties column of {ref}amdgpu-processor-table specifies Offset flat scratch:
If the kernel or any function it calls may use flat operations to access scratch memory, the prolog code must set up the FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI). Initialization uses Flat Scratch Init and Scratch Wavefront Offset SGPR registers (see {ref}amdgpu-amdhsa-initial-kernel-execution-state):
The low word of Flat Scratch Init is the 32-bit byte offset from SH_HIDDEN_PRIVATE_BASE_VIMID to the base of scratch backing memory being managed by SPI for the queue executing the kernel dispatch. This is the same value used in the Scratch Segment Buffer V# base address.
CP obtains this from the runtime. (The Scratch Segment Buffer base address is SH_HIDDEN_PRIVATE_BASE_VIMID plus this offset.)
The prolog must add the value of Scratch Wavefront Offset to get the wavefront's byte scratch backing memory offset from SH_HIDDEN_PRIVATE_BASE_VIMID.
The Scratch Wavefront Offset must also be used as an offset with Private segment address when using the Scratch Segment Buffer.
Since FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right shifted by 8 before moving into FLAT_SCRATCH_HI.
FLAT_SCRATCH_HI corresponds to SGPRn-4 on GFX7, and SGPRn-6 on GFX8 (where SGPRn is the highest numbered SGPR allocated to the wavefront). FLAT_SCRATCH_HI is multiplied by 256 (as it is in units of 256 bytes) and added to SH_HIDDEN_PRIVATE_BASE_VIMID to calculate the per wavefront FLAT SCRATCH BASE in flat memory instructions that access the scratch aperture.
The second word of Flat Scratch Init is 32-bit byte size of a single work-items scratch memory usage.
CP obtains this from the runtime, and it is always a multiple of DWORD. CP checks that the value in the kernel dispatch packet Private Segment Byte Size is not larger and requests the runtime to increase the queue's scratch size if necessary.
CP directly loads from the kernel dispatch packet Private Segment Byte Size field and rounds up to a multiple of DWORD. Having CP load it once avoids loading it at the beginning of every wavefront.
The kernel prolog code must move it to FLAT_SCRATCH_LO which is SGPRn-3 on GFX7 and SGPRn-5 on GFX8. FLAT_SCRATCH_LO is used as the FLAT SCRATCH SIZE in flat memory instructions.
If the Target Properties column of {ref}amdgpu-processor-table specifies Absolute flat scratch:
If the kernel or any function it calls may use flat operations to access scratch memory, the prolog code must set up the FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wavefront Offset SGPR registers (see {ref}amdgpu-amdhsa-initial-kernel-execution-state):
The Flat Scratch Init is the 64-bit address of the base of scratch backing memory being managed by SPI for the queue executing the kernel dispatch.
CP obtains this from the runtime.
The kernel prolog must add the value of the wave's Scratch Wavefront Offset and move the result as a 64-bit value to the FLAT_SCRATCH SGPR register pair which is SGPRn-6 and SGPRn-5. It is used as the FLAT SCRATCH BASE in flat memory instructions.
The Scratch Wavefront Offset must also be used as an offset with Private segment address when using the Scratch Segment Buffer (see {ref}amdgpu-amdhsa-kernel-prolog-private-segment-buffer).
If the Target Properties column of {ref}amdgpu-processor-table specifies Architected flat scratch:
If ENABLE_PRIVATE_SEGMENT is enabled in {ref}amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table then the FLAT_SCRATCH register pair will be initialized to the 64-bit address of the base of scratch backing memory being managed by SPI for the queue executing the kernel dispatch plus the value of the wave's Scratch Wavefront Offset for use as the flat scratch base in flat memory instructions.
(amdgpu-amdhsa-kernel-prolog-private-segment-buffer)=
If the Target Properties column of {ref}amdgpu-processor-table specifies Architected flat scratch then a Private Segment Buffer is not supported. Instead the flat SCRATCH instructions are used.
Otherwise, Private Segment Buffer SGPR register is used to initialize 4 SGPRs that are used as a V# to access scratch. CP uses the value provided by the runtime. It is used, together with Scratch Wavefront Offset as an offset, to access the private memory space using a segment address. See {ref}amdgpu-amdhsa-initial-kernel-execution-state.
The scratch V# is a four-aligned SGPR and always selected for the kernel as follows:
If it is known during instruction selection that there is stack usage, SGPR0-3 is reserved for use as the scratch V#. Stack usage is assumed if optimizations are disabled (-O0), if stack objects already exist (for locals, etc.), or if there are any function calls.
Otherwise, four high numbered SGPRs beginning at a four-aligned SGPR index are reserved for the tentative scratch V#. These will be used if it is determined that spilling is needed.
:::{note} This approach of using a tentative scratch V# and shifting the register numbers if used avoids having to perform register allocation a second time if the tentative V# is eliminated. This is more efficient and avoids the problem that the second register allocation may perform spilling which will fail as there is no longer a scratch V#. :::
When the kernel prolog code is being emitted it is known whether the scratch V# described above is actually used. If it is, the prolog code must set it up by copying the Private Segment Buffer to the scratch V# registers and then adding the Private Segment Wavefront Offset to the queue base address in the V#. The result is a V# with a base address pointing to the beginning of the wavefront scratch backing memory.
The Private Segment Buffer is always requested, but the Private Segment Wavefront Offset is only requested if it is used (see {ref}amdgpu-amdhsa-initial-kernel-execution-state).
(amdgpu-amdhsa-execution-barriers)=
See the {ref}barriers<amdgpu-execution-synchronization-barriers> section of the execution synchronization documentation.
(amdgpu-amdhsa-memory-model)=
This section describes the mapping of the LLVM memory model onto AMDGPU machine code (see {ref}memmodel).
The AMDGPU backend supports the memory synchronization scopes specified in {ref}amdgpu-memory-scopes.
:::{note} {ref}amdgpu-memmodel is a work in progress to provide a complete memory consistency model for AMDGPU, including newer features like availability, visibility and asynchronous operations. The new model will replace the model described in this section. Until then, this section should only be read along with the new model; any ambiguity is likely to be settled in favour of the new model. :::
The code sequences used to implement the memory model specify the order of instructions that a single thread must execute. The s_waitcnt and cache management instructions such as buffer_wbinvl1_vol are defined with respect to other memory instructions executed by the same thread. This allows them to be moved earlier or later which can allow them to be combined with other instances of the same instruction, or hoisted/sunk out of loops to improve performance. Only the instructions related to the memory model are given; additional s_waitcnt instructions are required to ensure registers are defined before being used. These may be able to be combined with the memory model s_waitcnt instructions as described above.
The AMDGPU backend supports the following memory models:
HSA Memory Model [{ref}HSA <hsa>]
: The HSA memory model uses a single happens-before relation for all address spaces (see {ref}amdgpu-address-spaces).
OpenCL Memory Model [{ref}OpenCL <opencl>]
: The OpenCL memory model which has separate happens-before relations for the global and local address spaces. Only a fence specifying both global and local address space, and seq_cst instructions join the relationships. Since the LLVM memfence instruction does not allow an address space to be specified the OpenCL fence has to conservatively assume both local and global address space was specified. However, optimizations can often be done to eliminate the additional s_waitcnt instructions when there are no intervening memory instructions which access the corresponding address space. The code sequences in the table indicate what can be omitted for the OpenCL memory. The target triple environment is used to determine if the source language is OpenCL (see {ref}amdgpu-opencl).
ds/flat_load/store/atomic instructions to local memory are termed LDS operations.
buffer/global/flat_load/store/atomic instructions to global memory are termed vector memory operations.
global_load_lds or buffer/global_load instructions with the lds flag are {ref}LDS DMA operations<amdgpu-dma-operations>.
Private address space uses buffer_load/store using the scratch V# (GFX6-GFX8), or scratch_load/store (GFX9-GFX11). Since only a single thread is accessing the memory, atomic memory orderings are not meaningful, and all accesses are treated as non-atomic.
Constant address space uses buffer/global_load instructions (or equivalent scalar memory instructions). Since the constant address space contents do not change during the execution of a kernel dispatch it is not legal to perform stores, and atomic memory orderings are not meaningful, and all accesses are treated as non-atomic.
A memory synchronization scope wider than work-group is not meaningful for the group (LDS) address space and is treated as work-group.
When a work-group's maximum flat work-group size does not exceed the wavefront size, the work-group fits within a single wavefront. So long as no LDSDMA operations occur, the LLVM workgroup synchronization scope is equivalent to its wavefront scope.
If the compiler can determine these conditions (e.g., through the function attributes amdgpu-flat-work-group-size and amdgpu-no-lds-dma), the AMDGPU backend optimizes workgroup scope operations by lowering them to wavefront-scoped machine instructions.
The memory model does not support the region address space which is treated as non-atomic.
The memory order also adds the single thread optimization constraints defined in table {ref}amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-table.
:::{list-table} AMDHSA Memory Model Single Thread Optimization Constraints :name: amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-table :header-rows: 2 :widths: auto
The code sequences used to implement the memory model are defined in the sections listed below.
Note: The presence of {ref}AV metadata<amdgpu-av-metadata> can suppress cache operations (such as write-back or invalidate) that are usually part of these sequences.
amdgpu-amdhsa-memory-model-gfx6-gfx9amdgpu-amdhsa-memory-model-gfx90aamdgpu-amdhsa-memory-model-gfx942amdgpu-amdhsa-memory-model-gfx10-gfx11amdgpu-amdhsa-memory-model-gfx12amdgpu-amdhsa-memory-model-gfx125x(amdgpu-amdhsa-execution-barriers-memory-model)=
:::{note} See {ref}amdgpu-execution-synchronization-barriers-execution-model for definitions of the terminology used in this section. :::
A can pair with a release fence program-ordered before it to form a barrier-arrive-release BR. The synchronization scope and the set of address spaces affected are determined by the release fence.W can pair with an acquire fence program-ordered after it to form a barrier-wait-acquire BA. The synchronization scope and the set of address spaces affected are determined by the acquire fence.A BR synchronizes-with BA in an address space AS if and only if:
A barrier-executes-before W.synchronization scope<amdgpu-memory-scopes> overlap.synchronization scope<amdgpu-memory-scopes> allow cross address space synchronization (they cannot have one-as) {sup}1.Informally, we can deduce from the above rules that:
{sup}1: This is a requirement due to how current hardware implements barrier operations. This limitation may be lifted in the future.
(amdgpu-fence-as)=
LLVM fences do not have address space information, thus, fence codegen usually needs to conservatively synchronize all address spaces.
In the case of OpenCL, where fences only need to synchronize user-specified address spaces, this can result in extra unnecessary waits. For instance, a fence that is supposed to only synchronize local memory will also have to wait on all global memory operations, which is unnecessary.
Memory Model Relaxation Annotations can be used as an optimization hint for fences to solve this problem. The AMDGPU backend recognizes the following tags on fences to control which address space a fence can synchronize:
amdgpu-synchronize-as:local - for the local address spaceamdgpu-synchronize-as:global- for the global address spaceMultiple tags can be used at the same time to synchronize with more than one address space.
:::{note} As an optimization hint, those tags are not guaranteed to survive until code generation. Optimizations are free to drop the tags to allow for better code optimization, at the cost of synchronizing additional address spaces. :::
(amdgpu-amdhsa-memory-model-gfx6-gfx9)=
For GFX6-GFX9:
s_waitcnt lgkmcnt(0) is required to ensure synchronization between LDS operations and vector memory operations between wavefronts of a work-group, but not between operations performed by the same wavefront.flat_load/store/atomic instructions can report out of vector memory order if they access LDS memory, and out of LDS operation order if they access global memory.buffer_wbinvl1_vol is required for coherence between wavefronts executing in different work-groups as they may be executing on different CUs.amdgpu-amdhsa-memory-spaces.s_waitcnt vmcnt(0) is required to ensure synchronization between vector memory operations of different CUs. It ensures a previous vector memory operation has completed before executing a subsequent vector memory or LDS operation and so can be used to meet the requirements of acquire and release.Scalar memory operations are only used to access memory that is proven to not change during the execution of the kernel dispatch. This includes constant address space and global address space for program scope const variables. Therefore, the kernel machine code does not have to maintain the scalar cache to ensure it is coherent with the vector caches. The scalar and vector caches are invalidated between kernel dispatches by CP since constant address space data may change between kernel dispatch executions. See {ref}amdgpu-amdhsa-memory-spaces.
The one exception is if scalar writes are used to spill SGPR registers. In this case the AMDGPU backend ensures the memory location used to spill is never accessed by vector memory operations at the same time. If scalar writes are used then a s_dcache_wb is inserted before the s_endpgm and before a function return since the locations may be used for vector memory instructions by a future wavefront that uses the same scratch area, or a function call that creates a frame at the same address, respectively. There is no need for a s_dcache_inv as all scalar writes are write-before-read in the same thread.
For kernarg backing memory:
*_vol.Scratch backing memory (which is used for the private address space) is accessed with MTYPE NC_NV (non-coherent non-volatile). Since the private address space is only accessed by a single thread, and is always write-before-read, there is never a need to invalidate these entries from the L1 cache. Hence all cache invalidates are done as *_vol to only invalidate the volatile cache lines.
A wave waiting on a s_barrier is unable to handle traps or exceptions, thus a s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) is required before entering the barrier so that no memory exception can occur during the barrier.
The code sequences used to implement the memory model for GFX6-GFX9 are defined in table {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table.
:::{list-table} AMDHSA Memory Model Code Sequences GFX6-GFX9 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table :header-rows: 1 :widths: auto
!volatile & !nontemporal
!volatile & nontemporal
volatile
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
!volatile & !nontemporal
!volatile & nontemporal
volatile
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
load atomic
acquire
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
load atomic
acquire
- Must happen before following buffer_wbinvl1_vol.
- Ensures the load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- If OpenCL omit lgkmcnt(0).
- Must happen before following buffer_wbinvl1_vol.
- Ensures the flat_load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local atomicrmw value being acquired.
atomicrmw
acquire
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acquire
none
- If OpenCL and address space is not generic, omit.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the value read by the fence-paired-atomic.
fence
acquire
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_wbinvl1_vol.
- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
store atomic
release
- If OpenCL, omit.
- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations to local have completed before performing the store that is being released.
store atomic
release
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations to memory have completed before performing the store that is being released.
atomicrmw
release
- If OpenCL, omit.
- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to local have completed before performing the atomicrmw that is being released.
atomicrmw
release
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and local have completed before performing the atomicrmw that is being released.
fence
release
none
- If OpenCL and address space is not generic, omit.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Must happen after any preceding local/generic load/load atomic/store/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations to local have completed before performing the following fence-paired-atomic.
fence
release
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
atomicrmw
acq_rel
- If OpenCL, omit.
- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to local have completed before performing the atomicrmw that is being released.
atomicrmw
acq_rel
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local load atomic value being acquired.
atomicrmw
acq_rel
- If OpenCL, omit.
- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to local have completed before performing the atomicrmw that is being released.
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
atomicrmw
acq_rel
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acq_rel
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acq_rel
none
- If OpenCL and address space is not generic, omit.
- However, since LLVM currently has no address space on the fence need to conservatively always generate (see comment for previous fence).
- Must happen after any preceding local/generic load/load atomic/store/store atomic/atomicrmw.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that all memory operations to local have completed before performing any following global memory operations.
- Ensures that the preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before following global memory operations. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
fence
acq_rel
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following buffer_wbinvl1_vol.
- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the cache. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data. This satisfies the requirements of acquire.
load atomic
seq_cst
- Must happen after preceding local/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent local memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
load atomic
seq_cst
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt lgkmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- s_waitcnt vmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
(amdgpu-amdhsa-memory-model-gfx90a)=
For GFX90A:
Each agent has multiple shader arrays (SA).
Each SA has multiple compute units (CU).
Each CU has multiple SIMDs that execute wavefronts.
The wavefronts for a single work-group are executed in the same CU but may be executed by different SIMDs. The exception is when in tgsplit execution mode when the wavefronts may be executed by different SIMDs in different CUs.
Each CU has a single LDS memory shared by the wavefronts of the work-groups executing on it. The exception is when in tgsplit execution mode when no LDS is allocated as wavefronts of the same work-group can be in different CUs.
All LDS operations of a CU are performed as wavefront wide operations in a global order and involve no caching. Completion is reported to a wavefront in execution order.
The LDS memory has multiple request queues shared by the SIMDs of a CU. Therefore, the LDS operations performed by different wavefronts of a work-group can be reordered relative to each other, which can result in reordering the visibility of vector memory operations with respect to LDS operations of other wavefronts in the same work-group. A s_waitcnt lgkmcnt(0) is required to ensure synchronization between LDS operations and vector memory operations between wavefronts of a work-group, but not between operations performed by the same wavefront.
The vector memory operations are performed as wavefront wide operations and completion is reported to a wavefront in execution order. The exception is that flat_load/store/atomic instructions can report out of vector memory order if they access LDS memory, and out of LDS operation order if they access global memory.
The vector memory operations access a single vector L1 cache shared by all SIMDs a CU. Therefore:
buffer_wbinvl1_vol is required as described in the following item.buffer_wbinvl1_vol is required for coherence between wavefronts executing in different work-groups as they may be executing on different CUs.The scalar memory operations access a scalar L1 cache shared by all wavefronts on a group of CUs. The scalar and vector L1 caches are not coherent. However, scalar operations are used in a restricted way so do not impact the memory model. See {ref}amdgpu-amdhsa-memory-spaces.
The vector and scalar memory operations use an L2 cache shared by all CUs on the same agent.
The L2 cache has independent channels to service disjoint ranges of virtual addresses.
Each CU has a separate request queue per channel. Therefore, the vector and scalar memory operations performed by wavefronts executing in different work-groups (which may be executing on different CUs), or the same work-group if executing in tgsplit mode, of an agent can be reordered relative to each other. A s_waitcnt vmcnt(0) is required to ensure synchronization between vector memory operations of different CUs. It ensures a previous vector memory operation has completed before executing a subsequent vector memory or LDS operation and so can be used to meet the requirements of acquire and release.
The L2 cache of one agent can be kept coherent with other agents by: using the MTYPE RW (read-write) or MTYPE CC (cache-coherent) with the PTE C-bit for memory local to the L2; and using the MTYPE NC (non-coherent) with the PTE C-bit set or MTYPE UC (uncached) for memory not local to the L2.
buffer_wbl2 is required. It will writeback dirty L2 cache lines of MTYPE RW (used for local coarse grain memory) and MTYPE NC ()used for remote coarse grain memory). Note that MTYPE CC (used for local fine grain memory) causes write through to DRAM, and MTYPE UC (used for remote fine grain memory) bypasses the L2, so both will never result in dirty L2 cache lines.buffer_invl2 is required. It will invalidate L2 cache lines with MTYPE NC (used for remote coarse grain memory). Note that MTYPE CC (used for local fine grain memory) and MTYPE RW (used for local coarse memory) cause local reads to be invalidated by remote writes with with the PTE C-bit so these cache lines are not invalidated. Note that MTYPE UC (used for remote fine grain memory) bypasses the L2, so will never result in L2 cache lines that need to be invalidated.PCIe access from the GPU to the CPU memory is kept coherent by using the MTYPE UC (uncached) which bypasses the L2.
Scalar memory operations are only used to access memory that is proven to not change during the execution of the kernel dispatch. This includes constant address space and global address space for program scope const variables. Therefore, the kernel machine code does not have to maintain the scalar cache to ensure it is coherent with the vector caches. The scalar and vector caches are invalidated between kernel dispatches by CP since constant address space data may change between kernel dispatch executions. See {ref}amdgpu-amdhsa-memory-spaces.
The one exception is if scalar writes are used to spill SGPR registers. In this case the AMDGPU backend ensures the memory location used to spill is never accessed by vector memory operations at the same time. If scalar writes are used then a s_dcache_wb is inserted before the s_endpgm and before a function return since the locations may be used for vector memory instructions by a future wavefront that uses the same scratch area, or a function call that creates a frame at the same address, respectively. There is no need for a s_dcache_inv as all scalar writes are write-before-read in the same thread.
For kernarg backing memory:
*_vol.Scratch backing memory (which is used for the private address space) is accessed with MTYPE NC_NV (non-coherent non-volatile). Since the private address space is only accessed by a single thread, and is always write-before-read, there is never a need to invalidate these entries from the L1 cache. Hence all cache invalidates are done as *_vol to only invalidate the volatile cache lines.
The code sequences used to implement the memory model for GFX90A are defined in table {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx90a-table.
:::{list-table} AMDHSA Memory Model Code Sequences GFX90A :name: amdgpu-amdhsa-memory-model-code-sequences-gfx90a-table :header-rows: 1 :widths: auto
!volatile & !nontemporal
!volatile & nontemporal
volatile
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
!volatile & !nontemporal
!volatile & nontemporal
volatile
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
load atomic
monotonic
- If not TgSplit execution mode, omit glc=1.
load atomic
monotonic
If TgSplit execution mode, local address space cannot be used.
store atomic
monotonic
If TgSplit execution mode, local address space cannot be used.
atomicrmw
monotonic
If TgSplit execution mode, local address space cannot be used.
load atomic
acquire
- If not TgSplit execution mode, omit glc=1.
- If not TgSplit execution mode, omit.
- Must happen before the following buffer_wbinvl1_vol.
- If not TgSplit execution mode, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale data.
load atomic
acquire
If TgSplit execution mode, local address space cannot be used.
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local load atomic value being acquired.
load atomic
acquire
- If not TgSplit execution mode, omit glc=1.
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_wbinvl1_vol and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
- Must happen before following buffer_wbinvl1_vol.
- Ensures the load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- Must happen before following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures the load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
load atomic
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL omit lgkmcnt(0).
- Must happen before following buffer_wbinvl1_vol.
- Ensures the flat_load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL omit lgkmcnt(0).
- Must happen before following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures the flat_load has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
atomicrmw
acquire
If TgSplit execution mode, local address space cannot be used.
atomicrmw
acquire
- If not TgSplit execution mode, omit.
- Must happen before the following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- If not TgSplit execution mode, omit.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
If TgSplit execution mode, local address space cannot be used.
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local atomicrmw value being acquired.
atomicrmw
acquire
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_wbinvl1_vol and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local atomicrmw value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- Must happen before following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
atomicrmw
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
fence
acquire
none
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/ atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_wbinvl1_vol and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the value read by the fence-paired-atomic.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acquire
none
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_wbinvl1_vol.
- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acquire
none
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
store atomic
release
If TgSplit execution mode, local address space cannot be used.
store atomic
release
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations have completed before performing the store that is being released.
store atomic
release
If TgSplit execution mode, local address space cannot be used.
store atomic
release
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations to memory have completed before performing the store that is being released.
store atomic
release
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations to memory and the L2 writeback have completed before performing the store that is being released.
atomicrmw
release
If TgSplit execution mode, local address space cannot be used.
atomicrmw
release
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
atomicrmw
release
If TgSplit execution mode, local address space cannot be used.
atomicrmw
release
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and local have completed before performing the atomicrmw that is being released.
atomicrmw
release
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to memory and the L2 writeback have completed before performing the store that is being released.
fence
release
none
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/load atomic/store/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
fence
release
none
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
fence
release
none
- If OpenCL and address space is local, omit.
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
atomicrmw
acq_rel
If TgSplit execution mode, local address space cannot be used.
atomicrmw
acq_rel
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- If not TgSplit execution mode, omit.
- Must happen before the following buffer_wbinvl1_vol.
- Ensures any following global data read is no older than the atomicrmw value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
If TgSplit execution mode, local address space cannot be used.
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local load atomic value being acquired.
atomicrmw
acq_rel
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- If not TgSplit execution mode, omit vmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_wbinvl1_vol and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acq_rel
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and L2 writeback have completed before performing the atomicrmw that is being released.
- Must happen before following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
atomicrmw
acq_rel
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acq_rel
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and L2 writeback have completed before performing the atomicrmw that is being released.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
fence
acq_rel
none
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- However, since LLVM currently has no address space on the fence need to conservatively always generate (see comment for previous fence).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/load atomic/store/store atomic/atomicrmw.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that all memory operations have completed before performing any following global memory operations.
- Ensures that the preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before following global memory operations. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before the following buffer_wbinvl1_vol.
- Ensures that the acquire-fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the acquire-fence-paired-atomic.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acq_rel
none
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following buffer_wbinvl1_vol.
- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the cache. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data. This satisfies the requirements of acquire.
fence
acq_rel
none
- If OpenCL and address space is local, omit.
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following buffer_invl2 and buffer_wbinvl1_vol.
- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the cache. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale L1 global data, nor see stale L2 MTYPE NC global data. MTYPE RW and CC memory will never be stale in L2 due to the memory probes.
load atomic
seq_cst
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- s_waitcnt lgkmcnt(0) must happen after preceding local/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- s_waitcnt vmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global/local memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
load atomic
seq_cst
If TgSplit execution mode, local address space cannot be used.
Same as corresponding load atomic acquire, except must generate all instructions even for OpenCL.
load atomic
seq_cst
- If TgSplit execution mode, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt lgkmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- s_waitcnt vmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
(amdgpu-amdhsa-memory-model-gfx942)=
For GFX942:
Each agent has multiple shader arrays (SA).
Each SA has multiple compute units (CU).
Each CU has multiple SIMDs that execute wavefronts.
The wavefronts for a single work-group are executed in the same CU but may be executed by different SIMDs. The exception is when in tgsplit execution mode when the wavefronts may be executed by different SIMDs in different CUs.
Each CU has a single LDS memory shared by the wavefronts of the work-groups executing on it. The exception is when in tgsplit execution mode when no LDS is allocated as wavefronts of the same work-group can be in different CUs.
All LDS operations of a CU are performed as wavefront wide operations in a global order and involve no caching. Completion is reported to a wavefront in execution order.
The LDS memory has multiple request queues shared by the SIMDs of a CU. Therefore, the LDS operations performed by different wavefronts of a work-group can be reordered relative to each other, which can result in reordering the visibility of vector memory operations with respect to LDS operations of other wavefronts in the same work-group. A s_waitcnt lgkmcnt(0) is required to ensure synchronization between LDS operations and vector memory operations between wavefronts of a work-group, but not between operations performed by the same wavefront.
The vector memory operations are performed as wavefront wide operations and completion is reported to a wavefront in execution order. The exception is that flat_load/store/atomic instructions can report out of vector memory order if they access LDS memory, and out of LDS operation order if they access global memory.
The vector memory operations access a single vector L1 cache shared by all SIMDs a CU. Therefore:
buffer_inv sc0 is required which will invalidate the L1 cache.buffer_inv sc0 is required to invalidate the L1 cache for coherence between wavefronts executing in different work-groups as they may be executing on different CUs.The scalar memory operations access a scalar L1 cache shared by all wavefronts on a group of CUs. The scalar and vector L1 caches are not coherent. However, scalar operations are used in a restricted way so do not impact the memory model. See {ref}amdgpu-amdhsa-memory-spaces.
The vector and scalar memory operations use an L2 cache.
The gfx942 can be configured as a number of smaller agents with each having a single L2 shared by all CUs on the same agent, or as fewer (possibly one) larger agents with groups of CUs on each agent each sharing separate L2 caches.
The L2 cache has independent channels to service disjoint ranges of virtual addresses.
Each CU has a separate request queue per channel for its associated L2. Therefore, the vector and scalar memory operations performed by wavefronts executing with different L1 caches and the same L2 cache can be reordered relative to each other.
A s_waitcnt vmcnt(0) is required to ensure synchronization between vector memory operations of different CUs. It ensures a previous vector memory operation has completed before executing a subsequent vector memory or LDS operation and so can be used to meet the requirements of acquire and release.
An L2 cache can be kept coherent with other L2 caches by using the MTYPE RW (read-write) for memory local to the L2, and MTYPE NC (non-coherent) with the PTE C-bit set for memory not local to the L2.
buffer_wbl2 is required. It does nothing if the agent is configured to have a single L2, or will writeback dirty L2 cache lines if configured to have multiple L2 caches.buffer_wbl2 sc1 is required. It will writeback dirty L2 cache lines.buffer_inv sc1 is required. It does nothing if the agent is configured to have a single L2, or will invalidate non-local L2 cache lines if configured to have multiple L2 caches.buffer_inv sc0 sc1 is required. It will invalidate non-local L2 cache lines if configured to have multiple L2 caches.PCIe access from the GPU to the CPU can be kept coherent by using the MTYPE UC (uncached) which bypasses the L2.
A buffer_inv with neither sc0 nor sc1 set (or BUFFER_INV 0 in MIR) does not invalidate the L1 or L2 caches. It is functionally s_nop with the side effect of incrementing vmcnt. This side effect is also present when EXEC is zero.
Scalar memory operations are only used to access memory that is proven to not change during the execution of the kernel dispatch. This includes constant address space and global address space for program scope const variables. Therefore, the kernel machine code does not have to maintain the scalar cache to ensure it is coherent with the vector caches. The scalar and vector caches are invalidated between kernel dispatches by CP since constant address space data may change between kernel dispatch executions. See {ref}amdgpu-amdhsa-memory-spaces.
The one exception is if scalar writes are used to spill SGPR registers. In this case the AMDGPU backend ensures the memory location used to spill is never accessed by vector memory operations at the same time. If scalar writes are used then a s_dcache_wb is inserted before the s_endpgm and before a function return since the locations may be used for vector memory instructions by a future wavefront that uses the same scratch area, or a function call that creates a frame at the same address, respectively. There is no need for a s_dcache_inv as all scalar writes are write-before-read in the same thread.
For kernarg backing memory:
*_vol.Scratch backing memory (which is used for the private address space) is accessed with MTYPE NC_NV (non-coherent non-volatile). Since the private address space is only accessed by a single thread, and is always write-before-read, there is never a need to invalidate these entries from the L1 cache. Hence all cache invalidates are done as *_vol to only invalidate the volatile cache lines.
The code sequences used to implement the memory model for GFX942 are defined in table {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx942-table.
:::{list-table} AMDHSA Memory Model Code Sequences GFX942 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx942-table :header-rows: 1 :widths: auto
!volatile & !nontemporal
!volatile & nontemporal
volatile
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
!volatile & !nontemporal
!volatile & nontemporal
volatile
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
load atomic
monotonic
If TgSplit execution mode, local address space cannot be used.
store atomic
monotonic
If TgSplit execution mode, local address space cannot be used.
atomicrmw
monotonic
If TgSplit execution mode, local address space cannot be used.
load atomic
acquire
- If not TgSplit execution mode, omit.
- Must happen before the following buffer_inv.
- If not TgSplit execution mode, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale data.
load atomic
acquire
If TgSplit execution mode, local address space cannot be used.
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local load atomic value being acquired.
load atomic
acquire
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_inv and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
- Must happen before following buffer_inv.
- Ensures the load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- Must happen before following buffer_inv.
- Ensures the load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale MTYPE NC global data. MTYPE RW and CC memory will never be stale due to the memory probes.
load atomic
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL omit lgkmcnt(0).
- Must happen before following buffer_inv.
- Ensures the flat_load has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL omit lgkmcnt(0).
- Must happen before the following buffer_inv.
- Ensures the flat_load has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale MTYPE NC global data. MTYPE RW and CC memory will never be stale due to the memory probes.
atomicrmw
acquire
If TgSplit execution mode, local address space cannot be used.
atomicrmw
acquire
- If not TgSplit execution mode, omit.
- Must happen before the following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the cache.
- If not TgSplit execution mode, omit.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
If TgSplit execution mode, local address space cannot be used.
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local atomicrmw value being acquired.
atomicrmw
acquire
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_inv and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local atomicrmw value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale MTYPE NC global data. MTYPE RW and CC memory will never be stale due to the memory probes.
atomicrmw
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale MTYPE NC global data. MTYPE RW and CC memory will never be stale due to the memory probes.
fence
acquire
none
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/ atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_inv and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the value read by the fence-paired-atomic.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acquire
none
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_inv.
- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acquire
none
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_inv.
- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
store atomic
release
If TgSplit execution mode, local address space cannot be used.
store atomic
release
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations have completed before performing the store that is being released.
store atomic
release
If TgSplit execution mode, local address space cannot be used.
store atomic
release
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at agent scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations to memory have completed before performing the store that is being released.
store atomic
release
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations to memory and the L2 writeback have completed before performing the store that is being released.
atomicrmw
release
If TgSplit execution mode, local address space cannot be used.
atomicrmw
release
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
atomicrmw
release
If TgSplit execution mode, local address space cannot be used.
atomicrmw
release
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at agent scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and local have completed before performing the atomicrmw that is being released.
atomicrmw
release
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to memory and the L2 writeback have completed before performing the store that is being released.
fence
release
none
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/load atomic/store/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
fence
release
none
- If OpenCL and address space is local, omit.
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at agent scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
fence
release
none
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
atomicrmw
acq_rel
If TgSplit execution mode, local address space cannot be used.
atomicrmw
acq_rel
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- If not TgSplit execution mode, omit.
- Must happen before the following buffer_inv.
- Ensures any following global data read is no older than the atomicrmw value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
If TgSplit execution mode, local address space cannot be used.
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local load atomic value being acquired.
atomicrmw
acq_rel
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL, omit lgkmcnt(0).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- If not TgSplit execution mode, omit vmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_inv and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at agent scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acq_rel
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and L2 writeback have completed before performing the atomicrmw that is being released.
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale MTYPE NC global data. MTYPE RW and CC memory will never be stale due to the memory probes.
atomicrmw
acq_rel
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at agent scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the cache.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acq_rel
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and L2 writeback have completed before performing the atomicrmw that is being released.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before following buffer_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale MTYPE NC global data. MTYPE RW and CC memory will never be stale due to the memory probes.
fence
acq_rel
none
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0).
- However, since LLVM currently has no address space on the fence need to conservatively always generate (see comment for previous fence).
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/ load atomic/store atomic/ atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/load atomic/store/store atomic/atomicrmw.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that all memory operations have completed before performing any following global memory operations.
- Ensures that the preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before following global memory operations. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before the following buffer_inv.
- Ensures that the acquire-fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the acquire-fence-paired-atomic.
- If not TgSplit execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acq_rel
none
- If OpenCL and address space is local, omit.
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at agent scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following buffer_inv.
- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the cache. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data. This satisfies the requirements of acquire.
fence
acq_rel
none
- If OpenCL and address space is local, omit.
- Must happen before following s_waitcnt.
- Performs L2 writeback to ensure previous global/generic store/atomicrmw are visible at system scope.
- If TgSplit execution mode, omit lgkmcnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/store/load atomic/store atomic/atomicrmw.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following buffer_inv.
- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the cache. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale MTYPE NC global data. MTYPE RW and CC memory will never be stale due to the memory probes.
load atomic
seq_cst
- Use lgkmcnt(0) if not TgSplit execution mode and vmcnt(0) if TgSplit execution mode.
- s_waitcnt lgkmcnt(0) must happen after preceding local/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- s_waitcnt vmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global/local memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
load atomic
seq_cst
If TgSplit execution mode, local address space cannot be used.
Same as corresponding load atomic acquire, except must generate all instructions even for OpenCL.
load atomic
seq_cst
- If TgSplit execution mode, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt lgkmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- s_waitcnt vmcnt(0) must happen after preceding global/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
(amdgpu-amdhsa-memory-model-gfx10-gfx11)=
For GFX10-GFX11:
s_waitcnt lgkmcnt(0) is required to ensure synchronization between LDS operations and vector memory operations between wavefronts of a work-group, but not between operations performed by the same wavefront.buffer_gl0_inv is required for coherence between wavefronts executing in the same work-group as they may be executing on SIMDs of different CUs that access different L0s. A buffer_gl0_inv is also required for coherence between wavefronts executing in different work-groups as they may be executing on different WGPs.amdgpu-amdhsa-memory-spaces.buffer_gl1_inv is required for coherence between wavefronts executing in different work-groups as they may be executing on different SAs that access different L1s.s_waitcnt vmcnt(0) & vscnt(0) is required to ensure synchronization between vector memory operations of different wavefronts. It ensures a previous vector memory operation has completed before executing a subsequent vector memory or LDS operation and so can be used to meet the requirements of acquire, release and sequential consistency.s_waitcnt vmcnt(0) & vscnt(0) is required to ensure synchronization between vector memory operations of different SAs. It ensures a previous vector memory operation has completed before executing a subsequent vector memory and so can be used to meet the requirements of acquire, release and sequential consistency.Scalar memory operations are only used to access memory that is proven to not change during the execution of the kernel dispatch. This includes constant address space and global address space for program scope const variables. Therefore, the kernel machine code does not have to maintain the scalar cache to ensure it is coherent with the vector caches. The scalar and vector caches are invalidated between kernel dispatches by CP since constant address space data may change between kernel dispatch executions. See {ref}amdgpu-amdhsa-memory-spaces.
The one exception is if scalar writes are used to spill SGPR registers. In this case the AMDGPU backend ensures the memory location used to spill is never accessed by vector memory operations at the same time. If scalar writes are used then a s_dcache_wb is inserted before the s_endpgm and before a function return since the locations may be used for vector memory instructions by a future wavefront that uses the same scratch area, or a function call that creates a frame at the same address, respectively. There is no need for a s_dcache_inv as all scalar writes are write-before-read in the same thread.
For kernarg backing memory:
Scratch backing memory (which is used for the private address space) is accessed with MTYPE NC (non-coherent). Since the private address space is only accessed by a single thread, and is always write-before-read, there is never a need to invalidate these entries from the L0 or L1 caches.
Wavefronts are executed in native mode with in-order reporting of loads and sample instructions. In this mode vmcnt reports completion of load, atomic with return and sample instructions in order, and the vscnt reports the completion of store and atomic without return in order. See MEM_ORDERED field in {ref}amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table.
Wavefronts can be executed in WGP or CU wavefront execution mode:
See WGP_MODE field in {ref}amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table and {ref}amdgpu-target-features.
The code sequences used to implement the memory model for GFX10-GFX11 are defined in table {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx10-gfx11-table.
:::{list-table} AMDHSA Memory Model Code Sequences GFX10-GFX11 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx10-gfx11-table :header-rows: 1 :widths: auto
!volatile & !nontemporal
!volatile & nontemporal
- If GFX10, omit dlc=1.
volatile
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
!volatile & !nontemporal
!volatile & nontemporal
- If GFX10, omit dlc=1.
volatile
- If GFX10, omit dlc=1.
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
load atomic
monotonic
- If CU wavefront execution mode, omit glc=1.
load atomic
monotonic
- If GFX11, omit dlc=1.
load atomic
acquire
- If CU wavefront execution mode, omit glc=1.
- If CU wavefront execution mode, omit.
- Must happen before the following buffer_gl0_inv and before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
- If OpenCL, omit.
- Must happen before the following buffer_gl0_inv and before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local load atomic value being acquired.
- If CU wavefront execution mode, omit.
- If OpenCL, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
- If CU wavefront execution mode, omit glc=1.
- If CU wavefront execution mode, omit vmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_gl0_inv and any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
- If GFX11, omit dlc=1.
- Must happen before following buffer_gl*_inv.
- Ensures the load has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- If GFX11, omit dlc=1.
- If OpenCL omit lgkmcnt(0).
- Must happen before following buffer_gl*_invl.
- Ensures the flat_load has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- If CU wavefront execution mode, omit.
- Use vmcnt(0) if atomic with return and vscnt(0) if atomic with no-return.
- Must happen before the following buffer_gl0_inv and before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
- If OpenCL, omit.
- Must happen before the following buffer_gl0_inv.
- Ensures any following global data read is no older than the local atomicrmw value being acquired.
- If OpenCL omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
- If CU wavefront execution mode, omit vm/vscnt(0).
- If OpenCL, omit lgkmcnt(0).
- Use vmcnt(0) if atomic with return and vscnt(0) if atomic with no-return.
- Must happen before the following buffer_gl0_inv.
- Ensures any following global data read is no older than a local atomicrmw value being acquired.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
- Use vmcnt(0) if atomic with return and vscnt(0) if atomic with no-return.
- Must happen before following buffer_gl*_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- If OpenCL, omit lgkmcnt(0).
- Use vmcnt(0) if atomic with return and vscnt(0) if atomic with no-return.
- Must happen before following buffer_gl*_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acquire
none
- If CU wavefront execution mode, omit vmcnt(0) and vscnt(0).
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0) and vscnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/ atomicrmw-with-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt vscnt(0) must happen after any preceding global/generic atomicrmw-no-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_gl0_inv.
- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acquire
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0) and vscnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load atomic/ atomicrmw-with-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt vscnt(0) must happen after any preceding global/generic atomicrmw-no-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Must happen before the following buffer_gl*_inv.
- Ensures that the fence-paired atomic has completed before invalidating the caches. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
store atomic
release
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations have completed before performing the store that is being released.
store atomic
release
- If OpenCL, omit.
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt vscnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- Must happen before the following store.
- Ensures that all global memory operations have completed before performing the store that is being released.
store atomic
release
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following store.
- Ensures that all memory operations have completed before performing the store that is being released.
atomicrmw
release
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
atomicrmw
release
- If OpenCL, omit.
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt vscnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- Must happen before the following store.
- Ensures that all global memory operations have completed before performing the store that is being released.
atomicrmw
release
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global and local have completed before performing the atomicrmw that is being released.
fence
release
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0) and vscnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/ atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
fence
release
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0) and vscnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
atomicrmw
acq_rel
- If OpenCL, omit lgkmcnt(0).
- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0), and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- Use vmcnt(0) if atomic with return and vscnt(0) if atomic with no-return.
- Must happen before the following buffer_gl0_inv.
- Ensures any following global data read is no older than the atomicrmw value being acquired.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
- If OpenCL, omit.
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt vscnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- Must happen before the following store.
- Ensures that all global memory operations have completed before performing the store that is being released.
- If OpenCL, omit.
- Must happen before the following buffer_gl0_inv.
- Ensures any following global data read is no older than the local load atomic value being acquired.
- If CU wavefront execution mode, omit.
- If OpenCL omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- If atomic with return, omit vscnt(0), if atomic with no-return, omit vmcnt(0).
- If OpenCL, omit lgkmcnt(0).
- Must happen before the following buffer_gl0_inv.
- Ensures any following global data read is no older than the load atomic value being acquired.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- Use vmcnt(0) if atomic with return and vscnt(0) if atomic with no-return.
- Must happen before following buffer_gl*_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acq_rel
- If OpenCL, omit lgkmcnt(0).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0), and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- If OpenCL, omit lgkmcnt(0).
- Use vmcnt(0) if atomic with return and vscnt(0) if atomic with no-return.
- Must happen before following buffer_gl*_inv.
- Ensures the atomicrmw has completed before invalidating the caches.
- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acq_rel
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0) and vscnt(0).
- However, since LLVM currently has no address space on the fence need to conservatively always generate (see comment for previous fence).
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/ atomicrmw.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that all memory operations have completed before performing any following global memory operations.
- Ensures that the preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before following global memory operations. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before the following buffer_gl0_inv.
- Ensures that the acquire-fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the acquire-fence-paired-atomic.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acq_rel
none
- If OpenCL and address space is not generic, omit lgkmcnt(0).
- If OpenCL and address space is local, omit vmcnt(0) and vscnt(0).
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.
- s_waitcnt vscnt(0) must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.
- s_waitcnt lgkmcnt(0) must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- Must happen before the following buffer_gl*_inv.
- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the caches. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data. This satisfies the requirements of acquire.
load atomic
seq_cst
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0), and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt lgkmcnt(0) must happen after preceding local/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- s_waitcnt vmcnt(0) must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- s_waitcnt vscnt(0) Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vscnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global/local memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
load atomic
seq_cst
- Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt vscnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt vmcnt(0) Must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- s_waitcnt vscnt(0) Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vscnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
load atomic
seq_cst
- Could be split into separate s_waitcnt vmcnt(0), s_waitcnt vscnt(0) and s_waitcnt lgkmcnt(0) to allow them to be independently moved according to the following rules.
- s_waitcnt lgkmcnt(0) must happen after preceding local load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt lgkmcnt(0) and so do not need to be considered.)
- s_waitcnt vmcnt(0) must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vmcnt(0) and so do not need to be considered.)
- s_waitcnt vscnt(0) Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own s_waitcnt vscnt(0) and so do not need to be considered.)
- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the s_waitcnt of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make the s_waitcnt be as late as possible so that the store may have already completed.)
(amdgpu-amdhsa-memory-model-gfx12)=
For GFX12:
Each agent has multiple shader arrays (SA).
Each SA has multiple work-group processors (WGP).
Each WGP has multiple compute units (CU).
Each CU has multiple SIMDs that execute wavefronts.
The wavefronts for a single work-group are executed in the same WGP.
Each WGP has a single LDS memory shared by the wavefronts of the work-groups executing on it.
All LDS operations of a WGP are performed as wavefront wide operations in a global order and involve no caching. Completion is reported to a wavefront in execution order.
The LDS memory has multiple request queues shared by the SIMDs of a WGP. Therefore, the LDS operations performed by different wavefronts of a work-group can be reordered relative to each other, which can result in reordering the visibility of vector memory operations with respect to LDS operations of other wavefronts in the same work-group. A s_wait_dscnt 0x0 is required to ensure synchronization between LDS operations and vector memory operations between wavefronts of a work-group, but not between operations performed by the same wavefront.
The vector memory operations are performed as wavefront wide operations. Vector memory operations are divided in different types. Completion of a vector memory operation is reported to a wavefront in-order within a type, but may be out of order between types. The types of vector memory operations (and their associated s_wait instructions) are:
s_wait_dscnts_wait_loadcnts_wait_storecnts_wait_samplecnts_wait_bvhcntVector and scalar memory instructions contain a SCOPE field with values corresponding to each cache level. The SCOPE determines whether a cache can complete an operation locally or whether it needs to forward the operation to the next cache level. The SCOPE values are:
SCOPE_CU: Compute Unit (NOTE: not affected by CU/WGP mode)SCOPE_SE: Shader EngineSCOPE_DEV: Device/AgentSCOPE_SYS: SystemWhen a memory operation with a given SCOPE reaches a cache with a smaller SCOPE value, it is forwarded to the next level of cache.
When a memory operation with a given SCOPE reaches a cache with a SCOPE value greater than or equal to its own, the operation can proceed:
global_inv, global_wb and global_wbinv instructions are used to invalidate, write-back and write-back+invalidate caches. The affected cache(s) are controlled by the SCOPE: of the instruction.
global_inv invalidates caches whose scope is strictly smaller than the instruction's. The invalidation requests cannot be reordered with pending or upcoming memory operations.
global_wb is a writeback operation that additionally ensures previous memory operation done at a lower scope level have reached the SCOPE: of the global_wb.
global_wb can be omitted for scopes other than SCOPE_SYS in gfx120x.The vector memory operations access a vector L0 cache. There is a single L0 cache per CU. Each SIMD of a CU accesses the same L0 cache. Therefore, no special action is required for coherence between the lanes of a single wavefront. To achieve coherence between wavefronts executing in the same work-group:
global_inv scope:SCOPE_SE is required as wavefronts may be executing on SIMDs of different CUs that access different L0s.The scalar memory operations access a scalar L0 cache shared by all wavefronts on a WGP. The scalar and vector L0 caches are not coherent. However, scalar operations are used in a restricted way so do not impact the memory model. See {ref}amdgpu-amdhsa-memory-spaces.
The vector and scalar memory L0 caches use an L1 buffer shared by all WGPs on the same SA. The L1 buffer acts as a bridge to L2 for clients within a SA.
The L1 buffers have independent quadrants to service disjoint ranges of virtual addresses.
Each L0 cache has a separate request queue per L1 quadrant. Therefore, the vector and scalar memory operations performed by different wavefronts, whether executing in the same or different work-groups (which may be executing on different CUs accessing different L0s), can be reordered relative to each other. Some or all of the wait instructions below are required to ensure synchronization between vector memory operations of different wavefronts. It ensures a previous vector memory operation has completed before executing a subsequent vector memory or LDS operation and so can be used to meet the requirements of acquire, release and sequential consistency.
s_wait_loadcnt 0x0s_wait_samplecnt 0x0s_wait_bvhcnt 0x0s_wait_storecnt 0x0The L1 buffers use an L2 cache shared by all SAs on the same agent.
The L2 cache has independent channels to service disjoint ranges of virtual addresses.
Each L1 quadrant of a single SA accesses a different L2 channel. Each L1 quadrant has a separate request queue per L2 channel. Therefore, the vector and scalar memory operations performed by wavefronts executing in different work-groups (which may be executing on different SAs) of an agent can be reordered relative to each other. Some or all of the wait instructions below are required to ensure synchronization between vector memory operations of different SAs. It ensures a previous vector memory operation has completed before executing a subsequent vector memory and so can be used to meet the requirements of acquire, release and sequential consistency.
s_wait_loadcnt 0x0s_wait_samplecnt 0x0s_wait_bvhcnt 0x0s_wait_storecnt 0x0The L2 cache can be kept coherent with other agents, or ranges of virtual addresses can be set up to bypass it to ensure system coherence.
A memory attached last level (MALL) cache exists for GPU memory. The MALL cache is fully coherent with GPU memory and has no impact on system coherence. All agents (GPU and CPU) access GPU memory through the MALL cache.
Scalar memory operations are only used to access memory that is proven to not change during the execution of the kernel dispatch. This includes constant address space and global address space for program scope const variables. Therefore, the kernel machine code does not have to maintain the scalar cache to ensure it is coherent with the vector caches. The scalar and vector caches are invalidated between kernel dispatches by CP since constant address space data may change between kernel dispatch executions. See {ref}amdgpu-amdhsa-memory-spaces.
For kernarg backing memory:
Scratch backing memory (which is used for the private address space) is accessed with MTYPE NC (non-coherent). Since the private address space is only accessed by a single thread, and is always write-before-read, there is never a need to invalidate these entries from L0.
Wavefronts can be executed in WGP or CU wavefront execution mode:
See WGP_MODE field in {ref}amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table and {ref}amdgpu-target-features.
The code sequences used to implement the memory model for GFX12 are defined in table {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx12-table.
The mapping of LLVM IR syncscope to GFX12 instruction scope operands is defined in {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
The table only applies if and only if it is directly referenced by an entry in {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx12-table, and it only applies to the instruction in the code sequence that references the table.
:::{list-table} AMDHSA Memory Model Code Sequences GFX12 - Instruction Scopes :name: amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table :header-rows: 1 :widths: auto
scope:SCOPE_SYSscope:SCOPE_SYSscope:SCOPE_SYSscope:SCOPE_SYSscope:SCOPE_DEVscope:SCOPE_DEVscope:SCOPE_SEscope:SCOPE_SYSscope:SCOPE_SYSscope:SCOPE_SYSscope:SCOPE_SYSscope:SCOPE_DEVscope:SCOPE_DEVscope:SCOPE_SE:::{list-table} AMDHSA Memory Model Code Sequences GFX12 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx12-table :header-rows: 1 :widths: auto
!volatile & !nontemporal
!volatile & nontemporal
th:TH_LOAD_NTvolatile
scope:SCOPE_SYSs_wait_loadcnt 0x0
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
!volatile & !nontemporal
!volatile & nontemporal
th:TH_STORE_NTvolatile
scope:SCOPE_SYSs_wait_storecnt 0x0
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
load atomic
monotonic
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
store atomic
monotonic
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
atomicrmw
monotonic
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
load atomic
acquire
scope:SCOPE_SE
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
s_wait_loadcnt 0x0
- If CU wavefront execution mode, omit.
- Must happen before the following
global_invand before any following global/generic load/load atomic/store/store atomic/atomicrmw.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
s_wait_dscnt 0x0
- If OpenCL, omit.
- Must happen before the following
global_invand before any following global/generic load/load atomic/store/store atomic/atomicrmw.- Ensures any following global data read is no older than the local load atomic value being acquired.
global_inv scope:SCOPE_SE
- If OpenCL or CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Must happen before the following
global_invand any following global/generic load/load atomic/store/store atomic/atomicrmw.- Ensures any following global data read is no older than a local load atomic value being acquired.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
s_wait_loadcnt 0x0
- Must happen before following
global_inv.- Ensures the load has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Must happen before following
global_inv.- Ensures the flat_load has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- If CU wavefront execution mode, omit.
- Must happen before the following
global_invand before any following global/generic load/load atomic/store/store atomic/atomicrmw.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
s_wait_dscnt 0x0
- If OpenCL, omit.
- Must happen before the following
global_inv.- Ensures any following global data read is no older than the local atomicrmw value being acquired.
global_inv scope:SCOPE_SE
- If OpenCL omit.
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_dscnt 0x0
- If CU wavefront execution mode, omit all for atomics without return, and only emit
s_wait_dscnt 0x0for atomics with return.- If OpenCL, omit
s_wait_dscnt 0x0- Must happen before the following
global_inv.- Ensures any following global data read is no older than a local atomicrmw value being acquired.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Must happen before following
global_inv.- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit dscnt
- Must happen before following global_inv
- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acquire
none
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Note: we don't have to use
s_wait_samplecnt 0x0ors_wait_bvhcnt 0x0because there are no atomic sample or BVH instructions that the fence could pair with.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load atomic/ atomicrmw-with-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_storecnt 0x0must happen after any preceding global/generic atomicrmw-no-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_dscnt 0x0must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).- Must happen before the following
global_inv.- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acquire
none
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- Note: we don't have to use
s_wait_samplecnt 0x0ors_wait_bvhcnt 0x0because there are no atomic sample or BVH instructions that the fence could pair with.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load atomic/ atomicrmw-with-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_storecnt 0x0must happen after any preceding global/generic atomicrmw-no-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_dscnt 0x0must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).- Must happen before the following
global_inv- Ensures that the fence-paired atomic has completed before invalidating the caches. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Ensures that following loads will not see stale data.
store atomic
release
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Ensures that all memory operations have completed before performing the store that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
store atomic
release
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.- Must happen before the following store.
- Ensures that all global memory operations have completed before performing the store that is being released.
store atomic
release
global_wb scope:SCOPE_SYS
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbif present, or any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following store.
- Ensures that all memory operations have completed before performing the store that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
atomicrmw
release
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- If OpenCL and CU wavefront execution mode, omit all.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomic.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
atomicrmw
release
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit all.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.- Must happen before the following atomic.
- Ensures that all global memory operations have completed before performing the store that is being released.
atomicrmw
release
global_wb scope:SCOPE_SYS
- If agent scope, omit.
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbif present, or any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomic.
- Ensures that all memory operations to global and local have completed before performing the atomicrmw that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.
fence
release
none
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/ atomicrmw.- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
fence
release
none
global_wb scope:SCOPE_SYS
- If agent scope, omit.
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0
- If OpenCl, omit
s_wait_dscnt 0x0.- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbif present, or any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
atomicrmw
acq_rel
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Must happen before the following
global_inv.- Ensures any following global data read is no older than the atomicrmw value being acquired.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
s_wait_loadcnt 0x0, s_wait_samplecnt 0x0 and s_wait_bvhcnt 0x0 must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0 must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.ds_atomic
s_wait_dscnt 0x0
- If OpenCL, omit.
- Must happen before the following
global_inv.- Ensures any following global data read is no older than the local load atomic value being acquired.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- If OpenCL omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_loadcnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Must happen before the following
global_inv.- Ensures any following global data read is no older than the load atomic value being acquired.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
atomicrmw
acq_rel
global_wb scope:SCOPE_SYS
- If agent scope, omit.
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbif present, or any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Must happen before following
global_inv.- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acq_rel
global_wb scope:SCOPE_SYS
- If agent scope, omit.
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbif present, or any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- Must happen before following
global_inv.- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
fence
acq_rel
none
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL and address space is not generic, omit
s_wait_dscnt 0x0- If OpenCL and address space is local, omit all but
s_wait_dscnt 0x0.- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/ atomicrmw.- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that all memory operations have completed before performing any following global memory operations.
- Ensures that the preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before following global memory operations. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Must happen before the following
global_inv.- Ensures that the acquire-fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the acquire-fence-paired-atomic.
global_inv scope:SCOPE_SE
- If CU wavefront execution mode, omit.
- Ensures that following loads will not see stale data.
fence
acq_rel
none
global_wb scope:SCOPE_SYS
- If agent scope, omit.
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL and address space is not generic, omit
s_wait_dscnt 0x0- If OpenCL and address space is local, omit all but
s_wait_dscnt 0x0.- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbif present, or any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following
global_inv- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the caches. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
global_inv scope:
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx12-scopes-table.- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data. This satisfies the requirements of acquire.
load atomic
seq_cst
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_dscnt 0x0must happen after preceding local/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_dscnt 0x0and so do not need to be considered.)s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own waits and so do not need to be considered.)s_wait_storecnt 0x0Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_storecnt 0x0and so do not need to be considered.)- Ensures any preceding sequential consistent global/local memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the
s_waits of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. Thes_waits could be placed after seq_store or before the seq_load. We choose the load to make thes_waits be as late as possible so that the store may have already completed.)
load atomic
seq_cst
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit all.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0Must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_waits and so do not need to be considered.)s_wait_storecnt 0x0Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_storecnt 0x0and so do not need to be considered.)- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the
s_waits of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make thes_waits be as late as possible so that the store may have already completed.)
load atomic
seq_cst
s_wait_bvhcnt 0x0s_wait_samplecnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_dscnt 0x0must happen after preceding local load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_dscnt 0x0and so do not need to be considered.)s_wait_loadcnt 0x0,s_wait_samplecnt 0x0ands_wait_bvhcnt 0x0must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_waits and so do not need to be considered.)s_wait_storecnt 0x0Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_storecnt 0x0and so do not need to be considered.)- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the
s_waits of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. Thes_waits could be placed after seq_store or before the seq_load. We choose the load to make thes_waits be as late as possible so that the store may have already completed.)
(amdgpu-amdhsa-memory-model-gfx125x)=
For GFX125x:
Device Structure:
Device Memory:
Each WGP has a single write-through WGP cache (WGP$) shared by the wavefronts of the work-groups executing on it. The WGP$ is divided between LDS and vector L0 memory.
Each WGP$ has two request queues; one per SIMD32-pair. Each queue can handle both LDS and vector L0 requests. Requests in one queue are executed serially and in-order, but are not kept in order with the other queue.
The scalar memory operations access a scalar L0 cache shared by all wavefronts on a WGP. The scalar and vector L0 caches are not kept coherent by hardware. However, scalar operations are used in a restricted way so do not impact the memory model. See {ref}amdgpu-amdhsa-memory-spaces.
The vector and scalar memory L0 caches are both clients of an L1 buffer shared by all WGPs on the same SE.
L1 buffers have separate request queues for each WGP$ it serves. Requests in one queue are executed serially and in-order, but are not kept in order with other queues.
L1 buffers are clients of the L2 cache.
There may be multiple L2 caches per agent. Ranges of virtual addresses can be set up as follows:
L2 caches have multiple memory channels to service disjoint ranges of virtual addresses.
Memory Model:
:::{note} This section is currently incomplete as work on the compiler is still ongoing. The following is a non-exhaustive list of unimplemented/undocumented features: non-volatile bit code sequences, globally accessing scratch atomics, multicast loads, barriers (including split barriers) and cooperative atomics. Scalar operations memory model needs more elaboration as well. :::
Vector memory operations are performed as wavefront wide operations, with the EXEC mask predicating which lanes execute.
Consecutive vector memory operations from the same wavefront are issued in program order. Vector memory operations are issued (and executed) in no particular order between wavefronts.
Wave execution of a vector memory operation instruction issues (initiates) the operation, but completion occurs an unspecified amount of time later. The s_wait_*cnt instructions must be used to determine if the operation has completed.
The types of vector memory operations (and their associated s_wait_*cnt instructions) are:
s_wait_loadcnts_wait_storecnts_wait_dscnts_wait_asynccnts_wait_tensorcnts_wait_xcnt is a counter that is incremented when a memory operation is issued, and decremented when memory address translation for that instruction is completed. Waiting on a memory counter s_wait_*cnt N also waits on s_wait_xcnt N.
s_wait_xcnt 0x0 is required before flat and global atomic stores/read-modify-write operations to guarantee atomicity during a xnack replay.Within a wavefront, vector memory operation completion (s_wait_*cnt decrement) is reported in order of issue within a type, but in no particular order between types.
Within a wavefront, the order in which data is returned to registers by a vector memory operation can be different from the order in which the vector memory operations were issued.
s_wait_*cnt instruction must be used to prevent multiple vector memory operations that return results to the same register from executing concurrently as they may not return their results in instruction issue order, even though they will be reported as completed in instruction issue order by the decrementing of the counter.Within a wavefront, consecutive loads and store to the same address will be processed in program order by the memory subsystem. Loads and stores to different addresses may be processed out of order with respect to a different address.
All non-ASYNC LDS vector memory operations of a WGP are performed as wavefront wide operations in a global order and involve no caching. Completion is reported to a wavefront in execution order.
ASYNC LDS and tensor vector memory operations are not covered by the memory model implemented by the AMDGPU backend. Neither s_wait_asynccnt nor s_wait_tensorcnt are inserted automatically. They must be emitted using compiler built-in calls.
Some vector memory operations contain a SCOPE field with values corresponding to each cache level. The SCOPE determines whether a cache can complete an operation locally or whether it needs to forward the operation to the next cache level. The SCOPE values are:
SCOPE_CU: WGPSCOPE_SE: Shader EngineSCOPE_DEV: Device/AgentSCOPE_SYS: SystemEach cache is assigned a SCOPE by the hardware depending on the agent's configuration.
SCOPE_DEV can always be used to implement agent coherence, even in the presence of multiple non-coherent L2 caches on the same agent.When a vector memory operation with a given SCOPE reaches a cache with a smaller SCOPE value, it is forwarded to the next level of cache.
When a vector memory operation with a given SCOPE reaches a cache with a SCOPE value greater than or equal to its own, the operation can proceed:
s_wait decrement) can be reported.Some memory operations contain a nv bit, for “non-volatile”, which indicates memory that is not expected to change during a kernel's execution. This information is propagated to the cache lines for that address (referred to as $nv).
nv=0 reads hit dirty $nv=1 data in cache, the hardware will writeback the data to the next level in the hierarchy and then subsequently read it again, updating the cache line with a clean $nv=0 copy of the data.global_inv, global_wb and global_wbinv are cache control instructions. The affected cache(s) are controlled by the SCOPE of the instruction. Only caches whose scope is strictly smaller than the instruction's are affected.
global_inv invalidates the data in affected caches so that subsequent reads will re-read from the next level in the cache hierarchy. The invalidation requests cannot be reordered with pending or upcoming memory operations. Instruction completion is reported using s_wait_loadcnt.global_wb flushes the dirty data in affected caches to the next level in the cache hierarchy. This instruction additionally ensures previous memory operation done at a lower scope level have reached the desired SCOPE:. Instruction completion is reported using s_wait_storecnt once all data has been acknowledged by the next level in the cache hierarchy.global_wbinv performs a global_inv then a global_wb. Instruction completion is reported using s_wait_storecnt.global_inv, global_wb and global_wbinv with nv=0 can only affect $nv=0 cache lines, whereas nv=1 can affect all cache lines.global_inv, global_wb and global_wbinv behave like memory operations issued to every address at the same time. They are kept in order with other memory operations from the same wave.global_load_monitor_* and flat_load_monitor_* instructions load data and request that the wave is notified (see s_monitor_sleep) if the L2 cache line that holds the data is evicted, or written to.
SCOPE of the instruction appropriately. The compiler may adjust the scope of the instruction accordingly to ensure this is the case.global_load_b32/64/128 with a global_load_monitor_b32/64/128 and a flat_load_b32/64/128 with a flat_load_monitor_b32/64/128.Scalar memory operations are only used to access memory that is proven to not change during the execution of the kernel dispatch. This includes constant address space and global address space for program scope const variables. Therefore, the kernel machine code does not have to maintain the scalar cache to ensure it is coherent with the vector caches. The scalar and vector caches are invalidated between kernel dispatches by CP since constant address space data may change between kernel dispatch executions. See {ref}amdgpu-amdhsa-memory-spaces.
Atomics in the scratch address space are handled as follows:
flat) address space. All properties of the atomic (atomic ordering, volatility, alignment, etc.) are preserved. Refer to the generic address space code sequences for further information.The code sequences used to implement the memory model for GFX125x are defined in table {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx125x-table.
The mapping of LLVM IR syncscope to GFX125x instruction scope operands is defined in {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
The table only applies if and only if it is directly referenced by an entry in {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx125x-table, and it only applies to the instruction in the code sequence that references the table.
:::{list-table} AMDHSA Memory Model Code Sequences GFX125x - Instruction Scopes :name: amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table :header-rows: 1 :widths: auto
scope:SCOPE_SYSscope:SCOPE_SYSscope:SCOPE_DEVscope:SCOPE_SEscope:SCOPE_CU [^scope-cu]scope:SCOPE_CU [^scope-cu]scope:SCOPE_CU [^scope-cu] :::[^scope-cu]: SCOPE_CU is the default scope: emitted by the compiler. It will be omitted when instructions are emitted in textual form by the compiler.
:::{list-table} AMDHSA Memory Model Code Sequences GFX125x :name: amdgpu-amdhsa-memory-model-code-sequences-gfx125x-table :header-rows: 1 :widths: auto
!volatile & !nontemporal
!volatile & nontemporal
th:TH_LOAD_NTvolatile
scope:SCOPE_SYSs_wait_loadcnt 0x0
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
!volatile & !nontemporal
!volatile & nontemporal
th:TH_STORE_NTvolatile
scope:SCOPE_SYSs_wait_storecnt 0x0
- Must happen before any following volatile global/generic load/store.
- Ensures that volatile operations to different addresses will not be reordered by hardware.
load atomic
monotonic
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
store atomic
monotonic
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
atomicrmw
monotonic
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_loadcnt 0x0
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
load atomic
acquire
s_wait_dscnt 0x0
- If OpenCL, omit.
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than the local load atomic value being acquired.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures any following global data read is no older than a local load atomic value being acquired.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_loadcnt 0x0
- Must happen before following
global_inv.- Ensures the load has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_loadcnt 0x0
- Must happen before following
global_inv.- Ensures the load has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
s_wait_loadcnt 0x0 must happen after global_inv and before subsequent memory operations.load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Must happen before following
global_inv.- Ensures the flat_load has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
load atomic
acquire
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Must happen before following
global_inv.- Ensures the flat_load has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
s_wait_loadcnt 0x0 must happen after global_inv and before subsequent memory operations.atomicrmw
acquire
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
atomicrmw
acquire
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
atomicrmw
acquire
s_wait_dscnt 0x0
- If OpenCL, omit.
- Ensures any following global data read is no older than the local atomicrmw value being acquired.
atomicrmw
acquire
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Ensures any following global data read is no older than the local atomicrmw value being acquired.
atomicrmw
acquire
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
globaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Must happen before following
global_inv.- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
globaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Must happen before following
global_inv.- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
s_wait_loadcnt 0x0 global_inv and before subsequent memory operations.atomicrmw
acquire
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit dscnt
- Must happen before following global_inv
- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
atomicrmw
acquire
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit dscnt
- Must happen before following global_inv
- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
s_wait_loadcnt 0x0 must happen after global_inv and before subsequent memory operations.fence
acquire
none
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load atomic/ atomicrmw-with-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_storecnt 0x0must happen after any preceding global/generic atomicrmw-no-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_dscnt 0x0must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).- Ensures that the fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
fence
acquire
none
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load atomic/ atomicrmw-with-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_storecnt 0x0must happen after any preceding global/generic atomicrmw-no-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_dscnt 0x0must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).- Must happen before the following
global_inv- Ensures that the fence-paired atomic has completed before invalidating the caches. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Ensures that following loads will not see stale data.
fence
acquire
none
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load atomic/ atomicrmw-with-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_storecnt 0x0must happen after any preceding global/generic atomicrmw-no-return-value with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).s_wait_dscnt 0x0must happen after any preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).- Must happen before the following
global_inv- Ensures that the fence-paired atomic has completed before invalidating the caches. Therefore any following locations read must be no older than the value read by the fence-paired-atomic.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Ensures that following loads will not see stale data.
s_wait_loadcnt 0x0 must happen after global_inv and before subsequent memory operations.store atomic
release
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
store atomic
release
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following store.
- Ensures that all memory operations have completed before performing the store that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
store atomic
release
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.- Must happen before the following store.
- Ensures that all global memory operations have completed before performing the store that is being released.
store atomic
release
s_wait_loadcnt 0x0s_wait_storecnt 0x0
The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.Must happen before the following
global_wb.Ensures that all global memory store/rmw operations have completed before their data is written back.
global_wb
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbor any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following store.
- Ensures that all memory operations have completed before performing the store that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
atomicrmw
release
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
atomicrmw
release
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomic.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
atomicrmw
release
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit all.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.- Must happen before the following atomic.
- Ensures that all global memory operations have completed before performing the store that is being released.
atomicrmw
release
s_wait_loadcnt 0x0s_wait_storecnt 0x0
The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.Must happen before the following
global_wb.Ensures that all global memory store/rmw operations have completed before their data is written back.
global_wb
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbor any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomic.
- Ensures that all memory operations to global and local have completed before performing the atomicrmw that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
fence
release
none
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/ atomicrmw.- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
fence
release
none
s_wait_loadcnt 0x0s_wait_storecnt 0x0
The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.Must happen before the following
global_wb.Ensures that all global memory store/rmw operations have completed before their data is written back.
global_wb
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0
- If OpenCl, omit
s_wait_dscnt 0x0.- If OpenCL and address space is local, omit all.
- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wbor any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before any following store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the fence-paired-atomic).
- Ensures that all memory operations have completed before performing the following fence-paired-atomic.
atomicrmw
acq_rel
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
atomicrmw
acq_rel
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- Must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
flatandglobaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Ensures any following global data read is no older than the atomicrmw value being acquired.
atomicrmw
acq_rel
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
s_wait_loadcnt 0x0 must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0 must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.ds_atomic
s_wait_dscnt 0x0
- If OpenCL, omit.
- Ensures any following global data read is no older than the local load atomic value being acquired.
atomicrmw
acq_rel
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_loadcnt 0x0.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- Ensures any following global data read is no older than the load atomic value being acquired.
atomicrmw
acq_rel
s_wait_loadcnt 0x0s_wait_storecnt 0x0
The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.Must happen before the following
global_wb.Ensures that all global memory store/rmw operations have completed before their data is written back.
global_wb
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wb.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations to global have completed before performing the atomicrmw that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Only needed for
globaloperations.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_loadcnt 0x0s_wait_storecnt 0x0
- Must happen before following
global_inv.- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
s_wait_loadcnt 0x0 must happen after global_inv and before subsequent memory operations.atomicrmw
acq_rel
s_wait_loadcnt 0x0s_wait_storecnt 0x0
The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.Must happen before the following
global_wb.Ensures that all global memory store/rmw operations have completed before their data is written back.
global_wb : - Apply {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wb.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following atomicrmw.
- Ensures that all memory operations have completed before performing the atomicrmw that is being released.
s_wait_xcnt 0x0
- Ensure operation remains atomic even during a xnack replay.
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- If atomic with return, use
th:TH_ATOMIC_RETURN.
s_wait_loadcnt 0x0s_wait_dscnt 0x0s_wait_storecnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0.- Must happen before following
global_inv.- Ensures the atomicrmw has completed before invalidating the caches.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/atomicrmw.
- Ensures that following loads will not see stale global data.
s_wait_loadcnt 0x0 must happen after global_inv and before subsequent memory operations.fence
acq_rel
none
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL and address space is not generic, omit
s_wait_dscnt 0x0- If OpenCL and address space is local, omit all but
s_wait_dscnt 0x0.- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/ atomicrmw.- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that all memory operations have completed before performing any following global memory operations.
- Ensures that the preceding local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before following global memory operations. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
- Ensures that the acquire-fence-paired atomic has completed before invalidating the cache. Therefore any following locations read must be no older than the value read by the acquire-fence-paired-atomic.
fence
acq_rel
none
s_wait_loadcnt 0x0s_wait_storecnt 0x0
The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic atomicrmw-with-return-value.s_wait_storecnt 0x0must happen after any preceding global/generic store/store atomic/ atomicrmw-no-return-value.Must happen before the following
global_wb.Ensures that all global memory store/rmw operations have completed before their data is written back.
global_wb : - Apply {ref}amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL and address space is not generic, omit
s_wait_dscnt 0x0- If OpenCL and address space is local, omit all but
s_wait_dscnt 0x0.- See {ref}
amdgpu-fence-asfor more details on fencing specific address spaces.- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after any preceding global/generic load/load atomic/ atomicrmw-with-return-value.s_wait_storecnt 0x0must happen afterglobal_wb.s_wait_dscnt 0x0must happen after any preceding local/generic load/store/load atomic/store atomic/atomicrmw.- Must happen before the following
global_inv- Ensures that the preceding global/local/generic load atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the acquire-fence-paired-atomic) has completed before invalidating the caches. This satisfies the requirements of acquire.
- Ensures that all previous memory operations have completed before a following global/local/generic store atomic/atomicrmw with an equal or wider sync scope and memory ordering stronger than unordered (this is termed the release-fence-paired-atomic). This satisfies the requirements of release.
global_inv
- Apply {ref}
amdgpu-amdhsa-memory-model-code-sequences-gfx125x-scopes-table.- Must happen before any following global/generic load/load atomic/store/store atomic/atomicrmw.
- Ensures that following loads will not see stale global data. This satisfies the requirements of acquire.
s_wait_loadcnt 0x0 must happen after global_inv and before subsequent memory operations.load atomic
seq_cst
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_dscnt 0x0must happen after preceding local/generic load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_dscnt 0x0and so do not need to be considered.)s_wait_loadcnt 0x0must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their own waits and so do not need to be considered.)s_wait_storecnt 0x0Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_storecnt 0x0and so do not need to be considered.)- Ensures any preceding sequential consistent global/local memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the
s_waits of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. Thes_waits could be placed after seq_store or before the seq_load. We choose the load to make thes_waits be as late as possible so that the store may have already completed.)
load atomic
seq_cst
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit all.
- The waits can be independently moved according to the following rules:
s_wait_loadcnt 0x0must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_waits and so do not need to be considered.)s_wait_storecnt 0x0Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_storecnt 0x0and so do not need to be considered.)- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the
s_waits of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. The s_waitcnt could be placed after seq_store or before the seq_load. We choose the load to make thes_waits be as late as possible so that the store may have already completed.)
load atomic
seq_cst
s_wait_storecnt 0x0s_wait_loadcnt 0x0s_wait_dscnt 0x0
- If OpenCL, omit
s_wait_dscnt 0x0- The waits can be independently moved according to the following rules:
s_wait_dscnt 0x0must happen after preceding local load atomic/store atomic/atomicrmw with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_dscnt 0x0and so do not need to be considered.)s_wait_loadcnt 0x0must happen after preceding global/generic load atomic/ atomicrmw-with-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_waits and so do not need to be considered.)s_wait_storecnt 0x0Must happen after preceding global/generic store atomic/ atomicrmw-no-return-value with memory ordering of seq_cst and with equal or wider sync scope. (Note that seq_cst fences have their owns_wait_storecnt 0x0and so do not need to be considered.)- Ensures any preceding sequential consistent global memory instructions have completed before executing this sequentially consistent instruction. This prevents reordering a seq_cst store followed by a seq_cst load. (Note that seq_cst is stronger than acquire/release as the reordering of load acquire followed by a store release is prevented by the
s_waits of the release, but there is nothing preventing a store release followed by load acquire from completing out of order. Thes_waits could be placed after seq_store or before the seq_load. We choose the load to make thes_waits be as late as possible so that the store may have already completed.)
(amdgpu-amdhsa-memory-model-gfx125x-cooperative-atomics)=
llvm.amdgcn.cooperative.atomic’ IntrinsicsThe collection of convergent threads participating in a cooperative atomic must belong to the same wave32.
Only naturally-aligned, contiguous groups of lanes may be used; see {ref}the table below<gfx125x-cooperative-atomic-intrinsics-table> for the set of possible lane groups. Cooperative atomics may be executed by more than one group per wave. Using an unsupported lane group, or using more lane groups per wave than the maximum will cause undefined behavior.
Using the intrinsic also causes undefined behavior if it loads or stores to addresses that:
:::{todo} Enumerate all cases where UB is invoked when using this intrinsic instead of hand-waving “specific global memory locations”. :::
:::{list-table} GFX125x Cooperative Atomic Intrinsics :name: gfx125x-cooperative-atomic-intrinsics-table :header-rows: 1
llvm.amdgcn.cooperative.atomic.store.32x4B0-31llvm.amdgcn.cooperative.atomic.load.32x4B0-31llvm.amdgcn.cooperative.atomic.store.16x8B0-15, 16-31llvm.amdgcn.cooperative.atomic.load.16x8B0-15, 16-31llvm.amdgcn.cooperative.atomic.store.8x16B0-7, 8-15, 16-23, 24-31llvm.amdgcn.cooperative.atomic.load.8x16B0-7, 8-15, 16-23, 24-31 :::(amdgpu-amdhsa-trap-handler-abi)=
For code objects generated by the AMDGPU backend for HSA [{ref}HSA <hsa>] compatible runtimes (see {ref}amdgpu-os), the runtime installs a trap handler that supports the s_trap instruction. For usage see:
{ref}amdgpu-trap-handler-for-amdhsa-os-v2-table
{ref}amdgpu-trap-handler-for-amdhsa-os-v3-table
{ref}amdgpu-trap-handler-for-amdhsa-os-v4-onwards-table
:::{list-table} AMDGPU Trap Handler for AMDHSA OS Code Object V2 :name: amdgpu-trap-handler-for-amdhsa-os-v2-table :header-rows: 1 :widths: auto
s_trap 0x00debugtrap(arg)
s_trap 0x01
SGPR0-1: : queue_ptr
VGPR0: : arg
Reserved for Finalizer HSA debugtrap intrinsic (not implemented).
llvm.traps_trap 0x02SGPR0-1: : queue_ptrllvm.debugtraps_trap 0x03s_trap 0x04s_trap 0x05s_trap 0x06s_trap 0x07s_trap 0x08s_trap 0xfes_trap 0xff%
:::{list-table} AMDGPU Trap Handler for AMDHSA OS Code Object V3 :name: amdgpu-trap-handler-for-amdhsa-os-v3-table :header-rows: 1 :widths: auto
s_trap 0x00s_trap 0x01llvm.traps_trap 0x02SGPR0-1: : queue_ptrllvm.debugtraps_trap 0x03s_trap 0x04s_trap 0x05s_trap 0x06s_trap 0x07s_trap 0x08s_trap 0xfes_trap 0xff%
:::{list-table} AMDGPU Trap Handler for AMDHSA OS Code Object V4 and Above :name: amdgpu-trap-handler-for-amdhsa-os-v4-onwards-table :header-rows: 1 :widths: auto
s_trap 0x00s_trap 0x01llvm.traps_trap 0x02SGPR0-1: : queue_ptrllvm.debugtraps_trap 0x03s_trap 0x04s_trap 0x05s_trap 0x06s_trap 0x07s_trap 0x08s_trap 0xfes_trap 0xff(amdgpu-amdhsa-function-call-convention)=
:::{note} This section is currently incomplete and has inaccuracies. It is WIP that will be updated as information is determined. :::
See {ref}amdgpu-dwarf-address-space-identifier for information on swizzled addresses. Unswizzled addresses are normal linear addresses.
(amdgpu-amdhsa-function-call-convention-kernel-functions)=
This section describes the call convention ABI for the outer kernel function.
See {ref}amdgpu-amdhsa-initial-kernel-execution-state for the kernel call convention.
The following is not part of the AMDGPU kernel calling convention but describes how the AMDGPU implements function calls:
Clang decides the kernarg layout to match the HSA Programmer's Language Reference [{ref}HSA <hsa>].
:::{todo}
amdgpu-amdhsa-kernel-prolog.(amdgpu-amdhsa-function-call-convention-non-kernel-functions)=
This section describes the call convention ABI for functions other than the outer kernel function.
If a kernel has function calls then scratch is always allocated and used for the call stack which grows from low address to high address using the swizzled scratch address space.
On entry to a function:
SGPR0-3 contain a V# with the following properties (see {ref}amdgpu-amdhsa-kernel-prolog-private-segment-buffer):
The FLAT_SCRATCH register pair is setup. See {ref}amdgpu-amdhsa-kernel-prolog-flat-scratch.
GFX6-GFX8: M0 register set to the size of LDS in bytes. See {ref}amdgpu-amdhsa-kernel-prolog-m0.
The EXEC register is set to the lanes active on entry to the function.
MODE register: the floating point rounding mode fields hold the mode requested by the program with llvm.set.rounding, or the default, round to nearest even. Other fields: TBD.
VGPR0-31 and SGPR4-29 are used to pass function input arguments as described below.
SGPR30-31 return address (RA). The code address that the function must return to when it completes. The value is undefined if the function is no return.
SGPR32 is used for the stack pointer (SP). It is an unswizzled scratch offset relative to the beginning of the wavefront scratch backing memory.
The unswizzled SP can be used with buffer instructions as an unswizzled SGPR offset with the scratch V# in SGPR0-3 to access the stack in a swizzled manner.
The unswizzled SP value can be converted into the swizzled SP value by:
swizzled SP = unswizzled SP / wavefront size
This may be used to obtain the private address space address of stack objects and to convert this address to a flat address by adding the flat scratch aperture base address.
The swizzled SP value is always 4-byte aligned for the r600 architecture and 16-byte aligned for the amdgcn architecture.
:::{note} The amdgcn value is selected to avoid dynamic stack alignment for the OpenCL language which has the largest base type defined as 16 bytes. :::
On entry, the swizzled SP value is the address of the first function argument passed on the stack. Other stack passed arguments are positive offsets from the entry swizzled SP value.
The function may use positive offsets beyond the last stack passed argument for stack allocated local variables and register spill slots. If necessary, the function may align these to greater alignment than 16 bytes. After these the function may dynamically allocate space for such things as runtime sized alloca local allocations.
If the function calls another function, it will place any stack allocated arguments after the last local allocation and adjust SGPR32 to the address after the last local allocation.
All other registers are unspecified.
Any necessary s_waitcnt has been performed to ensure memory is available to the function.
Use pass-by-reference (byref) instead of pass-by-value (byval) for struct arguments in C ABI. Callee is responsible for allocating stack memory and copying the value of the struct if modified. Note that the backend still supports byval for struct arguments.
On exit from a function:
VGPR0-31 and SGPR4-29 are used to pass function result arguments as described below. Any registers used are considered clobbered registers.
The following registers are preserved and have the same value as on entry:
FLAT_SCRATCH
EXEC
GFX6-GFX8: M0
All SGPR registers except the clobbered registers of SGPR4-31.
VGPR40-47
VGPR56-63
VGPR72-79
VGPR88-95
VGPR104-111
VGPR120-127
VGPR136-143
VGPR152-159
VGPR168-175
VGPR184-191
VGPR200-207
VGPR216-223
VGPR232-239
VGPR248-255
:::{note} Except the argument registers, the VGPRs clobbered and the preserved registers are intermixed at regular intervals in order to keep a similar ratio independent of the number of allocated VGPRs. :::
GFX90A: All AGPR registers except the clobbered registers AGPR0-31.
Lanes of all VGPRs that are inactive at the call site.
For the AMDGPU backend, an inter-procedural register allocation (IPRA) optimization may mark some of clobbered SGPR and VGPR registers as preserved if it can be determined that the called function does not change their value.
The PC is set to the RA provided on entry.
MODE register: as on entry to the function, unless the function changed the rounding mode on behalf of the program. Other fields: TBD.
All other registers are clobbered.
Any necessary s_waitcnt has been performed to ensure memory accessed by function is available to the caller.
:::{todo}
The function input arguments are made up of the formal arguments explicitly declared by the source language function plus the implicit input arguments used by the implementation.
The source language input arguments are:
this or self argument comes first as a pointer type.The source language result arguments are:
The source language input or result struct type arguments that are less than or equal to 16 bytes, are decomposed recursively into their base type fields, and each field is passed as if a separate argument. For input arguments, if the called function requires the struct to be in memory, for example because its address is taken, then the function body is responsible for allocating a stack location and copying the field arguments into it. Clang terms this direct struct.
The source language input struct type arguments that are greater than 16 bytes, are passed by reference. The caller is responsible for allocating a stack location to make a copy of the struct value and pass the address as the input argument. The called function is responsible to perform the dereference when accessing the input argument. Clang terms this by-value struct.
A source language result struct type argument that is greater than 16 bytes, is returned by reference. The caller is responsible for allocating a stack location to hold the result value and passes the address as the last input argument (before the implicit input arguments). In this case there are no result arguments. The called function is responsible to perform the dereference when storing the result value. Clang terms this structured return (sret).
TODO: correct the sret definition.
:::{todo} Is this definition correct? Or is sret only used if passing in registers, and pass as non-decomposed struct as stack argument? Or something else? Is the memory location in the caller stack frame, or a stack memory argument and so no address is passed as the caller can directly write to the argument stack location? But then the stack location is still live after return. If an argument stack location is it the first stack argument or the last one? :::
Lambda argument types are treated as struct types with an implementation defined set of fields.
:::{todo} Need to specify the ABI for lambda types for AMDGPU. :::
For AMDGPU backend all source language arguments (including the decomposed struct type arguments) are passed in VGPRs unless marked inreg in which case they are passed in SGPRs.
The AMDGPU backend walks the function call graph from the leaves to determine which implicit input arguments are used, propagating to each caller of the function. The used implicit arguments are appended to the function arguments after the source language arguments in the following order:
:::{todo} Is recursion or external functions supported? :::
Work-Item ID (1 VGPR)
The X, Y and Z work-item ID are packed into a single VGPR with the following layout. Only fields actually used by the function are set. The other bits are undefined.
The values come from the initial kernel execution state. See {ref}amdgpu-amdhsa-initial-kernel-execution-state.
:::{list-table} Work-item implicit argument layout :name: amdgpu-amdhsa-workitem-implicit-argument-layout-table :header-rows: 1
Dispatch Ptr (2 SGPRs)
The value comes from the initial kernel execution state. See {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
Queue Ptr (2 SGPRs)
The value comes from the initial kernel execution state. See {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
Kernarg Segment Ptr (2 SGPRs)
The value comes from the initial kernel execution state. See {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
Dispatch id (2 SGPRs)
The value comes from the initial kernel execution state. See {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
Work-Group ID X (1 SGPR)
The value comes from the initial kernel execution state. See {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
Work-Group ID Y (1 SGPR)
The value comes from the initial kernel execution state. See {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
Work-Group ID Z (1 SGPR)
The value comes from the initial kernel execution state. See {ref}amdgpu-amdhsa-sgpr-register-set-up-order-table.
Implicit Argument Ptr (2 SGPRs)
The value is computed by adding an offset to Kernarg Segment Ptr to get the global address space pointer to the first kernarg implicit argument.
The input and result arguments are assigned in order in the following manner:
:::{note} There are likely some errors and omissions in the following description that need correction.
:::{todo} Check the Clang source code to decipher how function arguments and return results are handled. Also see the AMDGPU specific values used. ::: :::
VGPR arguments are assigned to consecutive VGPRs starting at VGPR0 up to VGPR31.
If there are more arguments than will fit in these registers, the remaining arguments are allocated on the stack in order on naturally aligned addresses.
:::{todo} How are overly aligned structures allocated on the stack? :::
SGPR arguments are assigned to consecutive SGPRs starting at SGPR0 up to SGPR29.
If there are more arguments than will fit in these registers, the remaining arguments are allocated on the stack in order on naturally aligned addresses.
Note that decomposed struct type arguments may have some fields passed in registers and some in memory.
:::{todo} So, a struct which can pass some fields as decomposed register arguments, will pass the rest as decomposed stack elements? But an argument that will not start in registers will not be decomposed and will be passed as a non-decomposed stack value? :::
The following is not part of the AMDGPU function calling convention but describes how the AMDGPU implements function calls:
SGPR33 is used as a frame pointer (FP) if necessary. Like the SP it is an unswizzled scratch address. It is only needed if runtime sized alloca are used, or for the reasons defined in SIFrameLowering.
Runtime stack alignment is supported. SGPR34 is used as a base pointer (BP) to access the incoming stack arguments in the function. The BP is needed only when the function requires the runtime stack alignment.
Allocating SGPR arguments on the stack are not supported.
No CFI is currently generated. See {ref}amdgpu-dwarf-call-frame-information.
:::{note} CFI will be generated that defines the CFA as the unswizzled address relative to the wave scratch base in the unswizzled private address space of the lowest address stack allocated local variable.
DW_AT_frame_base will be defined as the swizzled address in the swizzled private address space by dividing the CFA by the wavefront size (since CFA is always at least dword aligned which matches the scratch swizzle element size).
If no dynamic stack alignment was performed, the stack allocated arguments are accessed as negative offsets relative to DW_AT_frame_base, and the local variables and register spill slots are accessed as positive offsets relative to DW_AT_frame_base. :::
Function argument passing is implemented by copying the input physical registers to virtual registers on entry. The register allocator can spill if necessary. These are copied back to physical registers at call sites. The net effect is that each function call can have these values in entirely distinct locations. The IPRA can help avoid shuffling argument registers.
Call sites are implemented by setting up the arguments at positive offsets from SP. Then SP is incremented to account for the known frame size before the call and decremented after the call.
:::{note} The CFI will reflect the changed calculation needed to compute the CFA from SP. :::
4-byte spill slots are used in the stack frame. One slot is allocated for an emergency spill slot. Buffer instructions are used for stack accesses and not the flat_scratch instruction.
:::{todo} Explain when the emergency spill slot is used. :::
:::{todo} Possible broken issues:
inreg for SGPR.sret is after this pointer.SCRATCH instruction could allow negative offsets, then can make FP be highest address of stack frame and use negative offset for locals. Would allow SP to be the same as FP and could support signal-handler-like as now have a real SP for the top of the stack.sret passed on the stack? In argument stack area? Can it overlay arguments? :::This section provides code conventions used when the target triple OS is amdpal (see {ref}amdgpu-target-triples).
(amdgpu-amdpal-code-object-metadata-section)=
:::{note} The metadata is currently in development and is subject to major changes. Only the current version is supported. When this document was generated the version was 2.6. :::
Code object metadata is specified by the NT_AMDGPU_METADATA note record (see {ref}amdgpu-note-records-v3-onwards).
The metadata is represented as Message Pack formatted binary data (see [{ref}MsgPack <msgpack>]). The top level is a Message Pack map that includes the keys defined in table {ref}amdgpu-amdpal-code-object-metadata-map-table and referenced tables.
Additional information can be added to the maps. To avoid conflicts, any key names should be prefixed by “vendor-name.” where vendor-name can be the name of the vendor and specific vendor tool that generates the information. The prefix is abbreviated to simply “.” when it appears within a map that has been added by the same vendor-name.
:::{list-table} AMDPAL Code Object Metadata Map :name: amdgpu-amdpal-code-object-metadata-map-table :header-rows: 1 :widths: auto
amdgpu-amdpal-code-object-pipeline-metadata-map-table for the definition of the keys included in that map. :::%
:::{list-table} AMDPAL Code Object Pipeline Metadata Map :name: amdgpu-amdpal-code-object-pipeline-metadata-map-table :header-rows: 1 :widths: auto
“.type”
string
Pipeline type, e.g. VsPs. Values include:
- “VsPs”
- “Gs”
- “Cs”
- “Ngg”
- “Tess”
- “GsTess”
- “NggTess”
amdgpu-amdpal-code-object-shader-map-table for the definition of the keys included in that map.amdgpu-amdpal-code-object-hardware-stage-map-table for the definition of the keys included in that map.amdgpu-amdpal-code-object-shader-function-map-table for the definition of the keys included in that map.amdgpu-amdpal-code-object-register-map-table for the definition of the keys included in that map.%
:::{list-table} AMDPAL Code Object Shader Map :name: amdgpu-amdpal-code-object-shader-map-table :header-rows: 1 :widths: auto
amdgpu-amdpal-code-object-api-shader-metadata-map-table for the definition of the keys included in that map. :::%
:::{list-table} AMDPAL Code Object API Shader Metadata Map :name: amdgpu-amdpal-code-object-api-shader-metadata-map-table :header-rows: 1 :widths: auto
“.hardware_mapping”
sequence of string
Required
Flags indicating the HW stages this API shader maps to. Values include:
- “.ls”
- “.hs”
- “.es”
- “.gs”
- “.vs”
- “.ps”
- “.cs” :::
%
:::{list-table} AMDPAL Code Object Hardware Stage Map :name: amdgpu-amdpal-code-object-hardware-stage-map-table :header-rows: 1 :widths: auto
amdgpu-amdpal-code-object-hardware-stage-metadata-map-table for the definition of the keys included in that map. :::%
:::{list-table} AMDPAL Code Object Hardware Stage Metadata Map :name: amdgpu-amdpal-code-object-hardware-stage-metadata-map-table :header-rows: 1 :widths: auto
%
:::{list-table} AMDPAL Code Object Shader Function Map :name: amdgpu-amdpal-code-object-shader-function-map-table :header-rows: 1 :widths: auto
amdgpu-amdpal-code-object-shader-function-metadata-map-table. :::%
:::{list-table} AMDPAL Code Object Shader Function Metadata Map :name: amdgpu-amdpal-code-object-shader-function-metadata-map-table :header-rows: 1 :widths: auto
“.shader_subtype”
string
Shader subtype/kind. Values include:
- “Unknown” :::
%
:::{list-table} AMDPAL Code Object Register Map :name: amdgpu-amdpal-code-object-register-map-table :header-rows: 1 :widths: auto
reg offsetreg offset is the dword offset into the GFXIP register space of a GRBM register (i.e., driver accessible GPU register number, not shader GPR register number). The driver is required to program each specified register to the corresponding specified value when executing this pipeline. Typically, the reg offsets are the uint16_t offsets to each register as defined by the hardware chip headers. The register is set to the provided value. However, a reg offset that specifies a user data register (e.g., COMPUTE_USER_DATA_0) needs special treatment. See {ref}amdgpu-amdpal-code-object-user-data-section section for more information. :::(amdgpu-amdpal-code-object-user-data-section)=
Each hardware stage has a set of 32-bit physical SPI user data registers (either 16 or 32 based on graphics IP and the stage) which can be written from a command buffer and then loaded into SGPRs when waves are launched via a subsequent dispatch or draw operation. This is the way most arguments are passed from the application/runtime to a hardware shader.
PAL abstracts this functionality by exposing a set of 128 user data entries per pipeline a client can use to pass arguments from a command buffer to one or more shaders in that pipeline. The ELF code object must specify a mapping from virtualized user data entries to physical user data registers, and PAL is responsible for implementing that mapping, including spilling overflow user data entries to memory if needed.
Since the user data registers are GRBM-accessible SPI registers, this mapping is actually embedded in the .registers metadata entry. For most registers, the value in that map is a literal 32-bit value that should be written to the register by the driver. However, when the register is a user data register (any USER_DATA register e.g., SPI_SHADER_USER_DATA_PS_5), the value is instead an encoding that tells the driver to write either a user data entry value or one of several driver-internal values to the register. This encoding is described in the following table:
:::{note} Currently, user data registers 0 and 1 (e.g., SPI_SHADER_USER_DATA_PS_0, and SPI_SHADER_USER_DATA_PS_1) are reserved. User data register 0 must always be programmed to the address of the GlobalTable, and user data register 1 must always be programmed to the address of the PerShaderTable. :::
%
:::{list-table} AMDPAL User Data Mapping :name: amdgpu-amdpal-code-object-metadata-user-data-mapping-table :header-rows: 1 :widths: auto
amdgpu-amdpal-code-object-metadata-user-data-per-shader-table-section for more detail (should always point to user data register 1).amdgpu-amdpal-code-object-metadata-user-data-spill-table-section for more detail.(amdgpu-amdpal-code-object-metadata-user-data-per-shader-table-section)=
Low 32 bits of the GPU address for an optional buffer in the .data section of the ELF. The high 32 bits of the address match the high 32 bits of the shader's program counter.
The buffer can be anything the shader compiler needs it for, and allows each shader to have its own region of the .data section. Typically, this could be a table of buffer SRD‘s and the data pointed to by the buffer SRD’s, but it could be a flat-address region of memory as well. Its layout and usage are defined by the shader compiler.
Each shader's table in the .data section is referenced by the symbol _amdgpu_xs_shdr_intrl_data where xs corresponds with the hardware shader stage the data is for. E.g., _amdgpu_cs_shdr_intrl_data for the compute shader hardware stage.
(amdgpu-amdpal-code-object-metadata-user-data-spill-table-section)=
It is possible for a hardware shader to need access to more user data entries than there are slots available in user data registers for one or more hardware shader stages. In that case, the PAL runtime expects the necessary user data entries to be spilled to GPU memory and use one user data register to point to the spilled user data memory. The value of the user data entry must then represent the location where a shader expects to read the low 32-bits of the table's GPU virtual address. The spill table itself represents a set of 32-bit values managed by the PAL runtime in GPU-accessible memory that can be made indirectly accessible to a hardware shader.
This section provides code conventions used when the target triple OS is empty (see {ref}amdgpu-target-triples).
For code objects generated by AMDGPU backend for non-amdhsa OS, the runtime does not install a trap handler. The llvm.trap and llvm.debugtrap instructions are handled as follows:
:::{list-table} AMDGPU Trap Handler for Non-AMDHSA OS :name: amdgpu-trap-handler-for-non-amdhsa-os-table :header-rows: 1 :widths: auto
This section describes the format of core files supporting AMDGPU. Core dumps for an AMDGPU program can come in 2 flavors: split or unified core files.
The split layout consists of one host core file containing the information to rebuild the image of the host process and one AMDGPU core file that contains the information for the AMDGPU agents used in the process. The AMDGPU core file consists of:
amdgpu_corefile_note).amdgpu_corefile_memory).The unified core file is the union of all the information contained in the two files of the split layout (all notes and load segments). It contains all the information required to reconstruct the image of the process across all the agents.
An AMDGPU core file is an ELF64 core file. The content of the header differs in unified core file layout and AMDGPU core file layout.
In the split files layout, the AMDGPU core file is an ELF64 file with the header configured as described in {ref}amdgpu-corefile-headers-table:
:::{list-table} AMDGPU corefile headers :name: amdgpu-corefile-headers-table :header-rows: 1 :widths: auto
e_ident[EI_CLASS]ELFCLASS64 (0x2)e_ident[EI_DATA]ELFDATA2LSB (0x1)e_ident[EI_OSABI]ELFOSABI_AMDGPU_HSA (0x40)e_typeET_CORE (0x4)e_ident[EI_ABIVERSION]ELFABIVERSION_AMDGPU_HSA_5e_machineEM_AMDGPU (0xe0) :::In the unified core file mode, the ELF64 headers are set to describe the host architecture and process.
(amdgpu_corefile_note)=
An AMDGPU core file must contain one snapshot note in a PT_NOTE segment. When using a split core file layout, this note is in the AMDGPU file.
The note record vendor field is “AMDGPU” and the record type is “NT_AMDGPU_KFD_CORE_STATE” (see {ref}amdgpu-note-records-v3-onwards)
The content of the note is defined in table {ref}amdgpu-core-snapshot-note-layout-table-v1:
:::{list-table} AMDGPU snapshot note format V1 :name: amdgpu-core-snapshot-note-layout-table-v1 :header-rows: 1 :widths: auto
version_majoruint32KFD_IOCTL_MAJOR_VERSIONversion_minoruint32KFD_IOCTL_MINOR_VERSIONruntime_info_sizeuint64n_agentsuint32agent_info_entry_sizeuint32n_queuesuint32queue_info_entry_sizeuint32runtime_infokfd_runtime_inforuntime_info_sizeagents_infokfd_dbg_device_info_entry[n_agents]n_agents * agent_info_entry_sizequeues_infokfd_queue_snapshot_entry[n_queues]n_queues * queue_info_entry_size:::
The definition of all the kfd_* types comes from the include/uapi/linux/kfd_ioctl.h header file from the KFD repository. It is usually installed in /usr/include/linux/kfd_ioctl.h. The version of the kfd_ioctl.h file used must define values for KFD_IOCTL_MAJOR_VERSION and KFD_IOCTL_MINOR_VERSION matching the values of kfd_version_major and kfd_version_major from the note.
(amdgpu_corefile_memory)=
An AMDGPU core file must contain an image of the AMDGPU agents' memory in load segments (of type PT_LOAD). Those segments must correspond to the memory regions where the content of the agent memory is mapped into the host process by the ROCr runtime (note that those memory mappings are usually not readable by the process itself).
When using the split core file layout, those segments must be included in the AMDGPU core file.
(amdgpu-opencl)=
When the language is OpenCL the following differences occur:
amdgpu-amdhsa-memory-model).opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table).amdgpu-amdhsa-code-object-metadata).:::{list-table} OpenCL kernel implicit arguments appended for AMDHSA OS :name: opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table :header-rows: 1 :widths: auto
(amdgpu-hcc)=
When the language is HCC the following differences occur:
amdgpu-amdhsa-memory-model).(amdgpu-assembler)=
AMDGPU backend has LLVM-MC based assembler which is currently in development. It supports AMDGCN GFX6-GFX11.
This section describes general syntax for instructions and operands.
An instruction has the following syntax:
<opcode> <operand0>, <operand1>,... <modifier0> <modifier1>...
Operands are comma-separated while modifiers are space-separated.
The order of operands and modifiers is fixed. Most modifiers are optional and may be omitted.
For more information about instructions, their semantics and supported combinations of operands, refer to one of instruction set architecture manuals [{ref}AMD-GCN-GFX6 <amd-gcn-gfx6>], [{ref}AMD-GCN-GFX7 <amd-gcn-gfx7>], [{ref}AMD-GCN-GFX8 <amd-gcn-gfx8>], [{ref}AMD-GCN-GFX900-GFX904-VEGA <amd-gcn-gfx900-gfx904-vega>], [{ref}AMD-GCN-GFX906-VEGA7NM <amd-gcn-gfx906-vega7nm>], [{ref}AMD-GCN-GFX908-CDNA1 <amd-gcn-gfx908-cdna1>], [{ref}AMD-GCN-GFX90A-CDNA2 <amd-gcn-gfx90a-cdna2>], [{ref}AMD-GCN-GFX942-CDNA3 <amd-gcn-gfx942-cdna3>], [{ref}AMD-GCN-GFX10-RDNA1 <amd-gcn-gfx10-rdna1>], [{ref}AMD-GCN-GFX10-RDNA2 <amd-gcn-gfx10-rdna2>], [{ref}AMD-GCN-GFX11-RDNA3 <amd-gcn-gfx11-rdna3>], [{ref}AMD-GCN-GFX11-RDNA3.5 <amd-gcn-gfx11-rdna3-5>] and [{ref}AMD-GCN-GFX12-RDNA4 <amd-gcn-gfx12-rdna4>].
Additionally, instruction syntax description can also be found at the ROCm LLVM Compiler Infrastructure website.
Detailed description of operands may be found here.
Detailed description of modifiers may be found here.
ds_add_u32 v2, v4 offset:16 ds_write_src2_b64 v2 offset0:4 offset1:8 ds_cmpst_f32 v2, v4, v6 ds_min_rtn_f64 v[8:9], v2, v[4:5]
For full list of supported instructions, refer to “LDS/GDS instructions” in ISA Manual.
flat_load_dword v1, v[3:4] flat_store_dwordx3 v[3:4], v[5:7] flat_atomic_swap v1, v[3:4], v5 glc flat_atomic_cmpswap v1, v[3:4], v[5:6] glc slc flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc
For full list of supported instructions, refer to “FLAT instructions” in ISA Manual.
buffer_load_dword v1, off, s[4:7], s1 buffer_store_dwordx4 v[1:4], v2, ttmp[4:7], s1 offen offset:4 glc tfe buffer_store_format_xy v[1:2], off, s[4:7], s1 buffer_wbinvl1 buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc
For full list of supported instructions, refer to “MUBUF Instructions” in ISA Manual.
s_load_dword s1, s[2:3], 0xfc s_load_dwordx8 s[8:15], s[2:3], s4 s_load_dwordx16 s[88:103], s[2:3], s4 s_dcache_inv_vol s_memtime s[4:5]
For full list of supported instructions, refer to “Scalar Memory Operations” in ISA Manual.
s_mov_b32 s1, s2 s_mov_b64 s[0:1], 0x80000000 s_cmov_b32 s1, 200 s_wqm_b64 s[2:3], s[4:5] s_bcnt0_i32_b64 s1, s[2:3] s_swappc_b64 s[2:3], s[4:5] s_cbranch_join s[4:5]
For full list of supported instructions, refer to “SOP1 Instructions” in ISA Manual.
s_add_u32 s1, s2, s3 s_and_b64 s[2:3], s[4:5], s[6:7] s_cselect_b32 s1, s2, s3 s_andn2_b32 s2, s4, s6 s_lshr_b64 s[2:3], s[4:5], s6 s_ashr_i32 s2, s4, s6 s_bfm_b64 s[2:3], s4, s6 s_bfe_i64 s[2:3], s[4:5], s6 s_cbranch_g_fork s[4:5], s[6:7]
For full list of supported instructions, refer to “SOP2 Instructions” in ISA Manual.
s_cmp_eq_i32 s1, s2 s_bitcmp1_b32 s1, s2 s_bitcmp0_b64 s[2:3], s4 s_setvskip s3, s5
For full list of supported instructions, refer to “SOPC Instructions” in ISA Manual.
s_barrier s_nop 2 s_endpgm s_waitcnt 0 ; Wait for all counters to be 0 s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0) ; Equivalent to above s_waitcnt vmcnt(1) ; Wait for vmcnt counter to be 1. s_sethalt 9 s_sleep 10 s_sendmsg 0x1 s_sendmsg sendmsg(MSG_INTERRUPT) s_trap 1
For full list of supported instructions, refer to “SOPP Instructions” in ISA Manual.
Unless otherwise mentioned, little verification is performed on the operands of SOPP Instructions, so it is up to the programmer to be familiar with the range or acceptable values.
For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA), the assembler will automatically use optimal encoding based on its operands. To force specific encoding, one can add a suffix to the opcode of the instruction:
VOP1/VOP2/VOP3/VOPC examples:
v_mov_b32 v1, v2 v_mov_b32_e32 v1, v2 v_nop v_cvt_f64_i32_e32 v[1:2], v2 v_floor_f32_e32 v1, v2 v_bfrev_b32_e32 v1, v2 v_add_f32_e32 v1, v2, v3 v_mul_i32_i24_e64 v1, v2, 3 v_mul_i32_i24_e32 v1, -3, v3 v_mul_i32_i24_e32 v1, -100, v3 v_addc_u32 v1, s[0:1], v2, v3, s[2:3] v_max_f16_e32 v1, v2, v3
VOP_DPP examples:
v_mov_b32 v0, v0 quad_perm:[0,2,1,1] v_sin_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 v_mov_b32 v0, v0 wave_shl:1 v_mov_b32 v0, v0 row_mirror v_mov_b32 v0, v0 row_bcast:31 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 v_add_f32 v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 v_max_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
VOP3_DPP examples (Available on GFX11+):
v_add_f32_e64_dpp v0, v1, v2 dpp8:[0,1,2,3,4,5,6,7] v_sqrt_f32_e64_dpp v0, v1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 v_ldexp_f32 v0, v1, v2 dpp8:[0,1,2,3,4,5,6,7]
VOP_SDWA examples:
v_mov_b32 v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD v_sin_f32 v0, v0 dst_unused:UNUSED_PAD src0_sel:WORD_1 v_fract_f32 v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
For full list of supported instructions, refer to “Vector ALU instructions”.
(amdgpu-amdhsa-assembler-predefined-symbols-v2)=
:::{warning} Code object V2 generation is no longer supported by this version of LLVM. :::
The AMDGPU assembler defines and updates some symbols automatically. These symbols do not affect code generation.
Set to the GFX major generation number of the target being assembled for. For example, when assembling for a “GFX9” target this will be set to the integer value “9”. The possible GFX major generation numbers are presented in {ref}amdgpu-processors.
Set to the GFX minor generation number of the target being assembled for. For example, when assembling for a “GFX810” target this will be set to the integer value “1”. The possible GFX minor generation numbers are presented in {ref}amdgpu-processors.
Set to the GFX stepping generation number of the target being assembled for. For example, when assembling for a “GFX704” target this will be set to the integer value “4”. The possible GFX stepping generation numbers are presented in {ref}amdgpu-processors.
Set to zero each time a {ref}amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel directive is encountered. At each instruction, if the current value of this symbol is less than or equal to the maximum VGPR number explicitly referenced within that instruction then the symbol value is updated to equal that VGPR number plus one.
Set to zero each time a {ref}amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel directive is encountered. At each instruction, if the current value of this symbol is less than or equal to the maximum VGPR number explicitly referenced within that instruction then the symbol value is updated to equal that SGPR number plus one.
(amdgpu-amdhsa-assembler-directives-v2)=
:::{warning} Code object V2 generation is no longer supported by this version of LLVM. :::
AMDGPU ABI defines auxiliary data in output code object. In assembly source, one can specify them with assembler directives.
major and minor are integers that specify the version of the HSA code object that will be generated by the assembler.
major, minor, and stepping are all integers that describe the instruction set architecture (ISA) version of the assembly program.
vendor and arch are quoted strings. vendor should always be equal to “AMD” and arch should always be equal to “AMDGPU”.
By default, the assembler will derive the ISA version, vendor, and arch from the value of the -mcpu option that is passed to the assembler.
(amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel)=
This directive specifies that the symbol with given name is a kernel entry point (label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.
This directive marks the beginning of a list of key / value pairs that are used to specify the amd_kernel_code_t object that will be emitted by the assembler. The list must be terminated by the .end_amd_kernel_code_t directive. For any amd_kernel_code_t values that are unspecified a default value will be used. The default value for all keys is 0, with the following exceptions:
-mcpu option that is passed to the assembler.wavefrontsize64 is enabled, otherwise 5. Note that wavefront size is specified as a power of two, so a value of n means a size of 2^ n.tgsplit is enabled for GFX90A onwards.cumode is disabled for GFX10 onwards.The .amd_kernel_code_t directive must be placed immediately after the function label and before any instructions.
For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document, comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.
(amdgpu-amdhsa-assembler-example-v2)=
:::{warning} Code object V2 generation is no longer supported by this version of LLVM. :::
Here is an example of a minimal assembly source file, defining one HSA kernel:
:number-lines: .hsa_code_object_version 1,0 .hsa_code_object_isa .hsatext .globl hello_world .p2align 8 .amdgpu_hsa_kernel hello_world hello_world: .amd_kernel_code_t enable_sgpr_kernarg_segment_ptr = 1 is_ptr64 = 1 compute_pgm_rsrc1_vgprs = 0 compute_pgm_rsrc1_sgprs = 0 compute_pgm_rsrc2_user_sgpr = 2 compute_pgm_rsrc1_wgp_mode = 0 compute_pgm_rsrc1_mem_ordered = 0 compute_pgm_rsrc1_fwd_progress = 1 .end_amd_kernel_code_t s_load_dwordx2 s[0:1], s[0:1] 0x0 v_mov_b32 v0, 3.14159 s_waitcnt lgkmcnt(0) v_mov_b32 v1, s0 v_mov_b32 v2, s1 flat_store_dword v[1:2], v0 s_endpgm .Lfunc_end0: .size hello_world, .Lfunc_end0-hello_world
(amdgpu-amdhsa-assembler-predefined-symbols-v3-onwards)=
The AMDGPU assembler defines and updates some symbols automatically. These symbols do not affect code generation.
Set to the GFX major generation number of the target being assembled for. For example, when assembling for a “GFX9” target this will be set to the integer value “9”. The possible GFX major generation numbers are presented in {ref}amdgpu-processors.
Set to the GFX minor generation number of the target being assembled for. For example, when assembling for a “GFX810” target this will be set to the integer value “1”. The possible GFX minor generation numbers are presented in {ref}amdgpu-processors.
Set to the GFX stepping generation number of the target being assembled for. For example, when assembling for a “GFX704” target this will be set to the integer value “4”. The possible GFX stepping generation numbers are presented in {ref}amdgpu-processors.
(amdgpu-amdhsa-assembler-symbol-next_free_vgpr)=
Set to zero before assembly begins. At each instruction, if the current value of this symbol is less than or equal to the maximum VGPR number explicitly referenced within that instruction then the symbol value is updated to equal that VGPR number plus one.
May be used to set the .amdhsa_next_free_vgpr directive in {ref}amdhsa-kernel-directives-table.
May be set at any time, e.g. manually set to zero at the start of each kernel.
(amdgpu-amdhsa-assembler-symbol-next_free_sgpr)=
Set to zero before assembly begins. At each instruction, if the current value of this symbol is less than or equal the maximum SGPR number explicitly referenced within that instruction then the symbol value is updated to equal that SGPR number plus one.
May be used to set the .amdhsa_next_free_spgr directive in {ref}amdhsa-kernel-directives-table.
May be set at any time, e.g. manually set to zero at the start of each kernel.
(amdgpu-amdhsa-assembler-directives-v3-onwards)=
Directives which begin with .amdgcn are valid for all amdgcn architecture processors, and are not OS-specific. Directives which begin with .amdhsa are specific to amdgcn architecture processors when the amdhsa OS is specified. See {ref}amdgpu-target-triples and {ref}amdgpu-processors.
(amdgpu-assembler-directive-amdgcn-target)=
Optional directive which declares the <target-triple>-<target-id> supported by the containing assembler source file. Used by the assembler to validate command-line options such as -triple, -mcpu, and --offload-arch=<target-id>. A non-canonical target ID is allowed. See {ref}amdgpu-target-triples and {ref}amdgpu-target-id.
:::{note} The target ID syntax used for code object V2 to V3 for this directive differs from that used elsewhere. See {ref}amdgpu-target-id-v2-v3. :::
(amdgpu-assembler-directive-amdhsa-code-object-version)=
Optional directive which declares the code object version to be generated by the assembler. If not present, a default value will be used.
Creates a correctly aligned AMDHSA kernel descriptor and a symbol, <name>.kd, in the current location of the current section. Only valid when the OS is amdhsa. <name> must be a symbol that labels the first instruction to execute, and does not need to be previously defined.
Marks the beginning of a list of directives used to generate the bytes of a kernel descriptor, as described in {ref}amdgpu-amdhsa-kernel-descriptor. Directives which may appear in this list are described in {ref}amdhsa-kernel-directives-table. Directives may appear in any order, must be valid for the target being assembled for, and cannot be repeated. Directives support the range of values specified by the field they reference in {ref}amdgpu-amdhsa-kernel-descriptor. If a directive is not specified, it is assumed to have its default value, unless it is marked as “Required”, in which case it is an error to omit the directive. This list of directives is terminated by an .end_amdhsa_kernel directive.
:::{list-table} AMDHSA Kernel Assembler Directives :name: amdhsa-kernel-directives-table :header-rows: 1 :widths: auto
.amdhsa_group_segment_fixed_sizeamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_private_segment_fixed_sizeamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_kernarg_sizeamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_countamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table.amdhsa_user_sgpr_private_segment_bufferamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_dispatch_ptramdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_queue_ptramdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_kernarg_segment_ptramdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_dispatch_idamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_flat_scratch_initamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_private_segment_sizeamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_wavefront_size32amdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_uses_dynamic_stackamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_named_barrier_countamdgpu-amdhsa-compute_pgm_rsrc3-gfx12-table..amdhsa_system_sgpr_private_segment_wavefront_offsetamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_enable_private_segmentamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_system_sgpr_workgroup_id_xamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_system_sgpr_workgroup_id_yamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_system_sgpr_workgroup_id_zamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_system_sgpr_workgroup_infoamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_system_vgpr_workitem_idamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table. Possible values are defined in {ref}amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table..amdhsa_next_free_vgpramdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_next_free_sgpramdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_accum_offsetamdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table..amdhsa_reserve_vccamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_reserve_flat_scratchamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_reserve_xnack_maskamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_float_round_mode_32amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table. Possible values are defined in {ref}amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table..amdhsa_float_round_mode_16_64amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table. Possible values are defined in {ref}amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table..amdhsa_float_denorm_mode_32amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table. Possible values are defined in {ref}amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table..amdhsa_float_denorm_mode_16_64amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table. Possible values are defined in {ref}amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table..amdhsa_dx10_clampamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_ieee_modeamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_round_robin_schedulingamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_fp16_overflowamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_tg_splitamdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table..amdhsa_workgroup_processor_modeamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_memory_orderedamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_forward_progressamdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table..amdhsa_shared_vgpr_countamdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table..amdhsa_inst_pref_sizeamdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table or {ref}amdgpu-amdhsa-compute_pgm_rsrc3-gfx12-table.amdhsa_exception_fp_ieee_invalid_opamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_exception_fp_denorm_srcamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_exception_fp_ieee_div_zeroamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_exception_fp_ieee_overflowamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_exception_fp_ieee_underflowamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_exception_fp_ieee_inexactamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_exception_int_div_zeroamdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table..amdhsa_user_sgpr_kernarg_preload_lengthamdgpu-amdhsa-kernel-descriptor-v3-table..amdhsa_user_sgpr_kernarg_preload_offsetamdgpu-amdhsa-kernel-descriptor-v3-table. :::Optional directive which declares the contents of the NT_AMDGPU_METADATA note record (see {ref}amdgpu-elf-note-records-table-v3-onwards).
The contents must be in the [{ref}YAML <yaml>] markup format, with the same structure and semantics described in {ref}amdgpu-amdhsa-code-object-metadata-v3, {ref}amdgpu-amdhsa-code-object-metadata-v4 or {ref}amdgpu-amdhsa-code-object-metadata-v5.
This directive is terminated by an .end_amdgpu_metadata directive.
(amdgpu-assembler-directive-amdgpu-info)=
Begins a per-function metadata block for <symbol> in the .amdgpu.info section (see {ref}amdgpu-info-section). Only valid when the OS is amdhsa. The block is terminated by an .end_amdgpu_info directive.
The following sub-directives may appear inside the block:
:::{list-table} .amdgpu_info Sub-Directives :name: amdgpu-info-sub-directives-table :header-rows: 1 :widths: auto
.amdgpu_flags valueFuncInfoFlags bitfield (u32).amdgpu_num_sgpr value.amdgpu_num_vgpr value.amdgpu_num_agpr value.amdgpu_private_segment_size n.amdgpu_use symbol.amdgpu_call symbol.amdgpu_indirect_call “type-id”.amdgpu_typeid “type-id”Example:
.amdgpu_info my_kernel .amdgpu_flags 7 .amdgpu_num_sgpr 33 .amdgpu_num_vgpr 32 .amdgpu_num_agpr 0 .amdgpu_private_segment_size 0 .amdgpu_use lds_var .amdgpu_call helper .amdgpu_indirect_call "vi" .end_amdgpu_info
(amdgpu-amdhsa-assembler-example-v3-onwards)=
Here is an example of a minimal assembly source file, defining one HSA kernel:
:number-lines: .amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional .text .globl hello_world .p2align 8 .type hello_world,@function hello_world: s_load_dwordx2 s[0:1], s[0:1] 0x0 v_mov_b32 v0, 3.14159 s_waitcnt lgkmcnt(0) v_mov_b32 v1, s0 v_mov_b32 v2, s1 flat_store_dword v[1:2], v0 s_endpgm .Lfunc_end0: .size hello_world, .Lfunc_end0-hello_world .rodata .p2align 6 .amdhsa_kernel hello_world .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr .end_amdhsa_kernel .amdgpu_metadata --- amdhsa.version: - 1 - 0 amdhsa.kernels: - .name: hello_world .symbol: hello_world.kd .kernarg_segment_size: 48 .group_segment_fixed_size: 0 .private_segment_fixed_size: 0 .kernarg_segment_align: 4 .wavefront_size: 64 .sgpr_count: 2 .vgpr_count: 3 .max_flat_workgroup_size: 256 .args: - .size: 8 .offset: 0 .value_kind: global_buffer .address_space: global .actual_access: write_only //... .end_amdgpu_metadata
This kernel is equivalent to the following HIP program:
:number-lines: __global__ void hello_world(float *p) { *p = 3.14159f; }
If an assembly source file contains multiple kernels and/or functions, the {ref}amdgpu-amdhsa-assembler-symbol-next_free_vgpr and {ref}amdgpu-amdhsa-assembler-symbol-next_free_sgpr symbols may be reset using the .set <symbol>, <expression> directive. For example, in the case of two kernels, where function1 is only called from kernel1 it is sufficient to group the function with the kernel that calls it and reset the symbols between the two connected components:
:number-lines: .amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional // gpr tracking symbols are implicitly set to zero .text .globl kern0 .p2align 8 .type kern0,@function kern0: // ... s_endpgm .Lkern0_end: .size kern0, .Lkern0_end-kern0 .rodata .p2align 6 .amdhsa_kernel kern0 // ... .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr .end_amdhsa_kernel // reset symbols to begin tracking usage in func1 and kern1 .set .amdgcn.next_free_vgpr, 0 .set .amdgcn.next_free_sgpr, 0 .text .hidden func1 .global func1 .p2align 2 .type func1,@function func1: // ... s_setpc_b64 s[30:31] .Lfunc1_end: .size func1, .Lfunc1_end-func1 .globl kern1 .p2align 8 .type kern1,@function kern1: // ... s_getpc_b64 s[4:5] s_add_u32 s4, s4, func1@rel32@lo+4 s_addc_u32 s5, s5, func1@rel32@lo+4 s_swappc_b64 s[30:31], s[4:5] // ... s_endpgm .Lkern1_end: .size kern1, .Lkern1_end-kern1 .rodata .p2align 6 .amdhsa_kernel kern1 // ... .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr .end_amdhsa_kernel
These symbols cannot identify connected components in order to automatically track the usage for each kernel. However, in some cases careful organization of the kernels and functions in the source file means there is minimal additional effort required to accurately calculate GPR usage.
(amd-gcn-gfx6)= [AMD-GCN-GFX6] AMD Southern Islands Series ISA
(amd-gcn-gfx7)= [AMD-GCN-GFX7] AMD Sea Islands Series ISA
(amd-gcn-gfx8)= [AMD-GCN-GFX8] AMD GCN3 Instruction Set Architecture
(amd-gcn-gfx900-gfx904-vega)= [AMD-GCN-GFX900-GFX904-VEGA] AMD Vega Instruction Set Architecture
(amd-gcn-gfx906-vega7nm)= [AMD-GCN-GFX906-VEGA7NM] AMD Vega 7nm Instruction Set Architecture
(amd-gcn-gfx908-cdna1)= [AMD-GCN-GFX908-CDNA1] AMD Instinct MI100 Instruction Set Architecture
(amd-gcn-gfx90a-cdna2)= [AMD-GCN-GFX90A-CDNA2] AMD Instinct MI200 Instruction Set Architecture
(amd-gcn-gfx942-cdna3)= [AMD-GCN-GFX942-CDNA3] AMD Instinct MI300 Instruction Set Architecture
(amd-gcn-gfx10-rdna1)= [AMD-GCN-GFX10-RDNA1] AMD RDNA 1.0 Instruction Set Architecture
(amd-gcn-gfx10-rdna2)= [AMD-GCN-GFX10-RDNA2] AMD RDNA 2 Instruction Set Architecture
(amd-gcn-gfx11-rdna3)= [AMD-GCN-GFX11-RDNA3] AMD RDNA 3 Instruction Set Architecture
(amd-gcn-gfx11-rdna3-5)= [AMD-GCN-GFX11-RDNA3.5] AMD RDNA 3.5 Instruction Set Architecture
(amd-gcn-gfx12-rdna4)= [AMD-GCN-GFX12-RDNA4] AMD RDNA 4 Instruction Set Architecture
(amd-radeon-hd-2000-3000)= [AMD-RADEON-HD-2000-3000] AMD R6xx shader ISA
(amd-radeon-hd-4000)= [AMD-RADEON-HD-4000] AMD R7xx shader ISA
(amd-radeon-hd-5000)= [AMD-RADEON-HD-5000] AMD Evergreen shader ISA
(amd-radeon-hd-6000)= [AMD-RADEON-HD-6000] AMD Cayman/Trinity shader ISA
(amd-rocm)= [AMD-ROCm] AMD ROCm™ Platform
(amd-rocm-github)= [AMD-ROCm-github] AMD ROCm™ github
(amd-rocm-release-notes)= [AMD-ROCm-Release-Notes] AMD ROCm Release Notes
(clang-attr)= [CLANG-ATTR] Attributes in Clang
(dwarf)= [DWARF] DWARF Debugging Information Format
(elf)= [ELF] Executable and Linkable Format (ELF)
(hrf)= [HRF] Heterogeneous-race-free Memory Models
(hsa)= [HSA] Heterogeneous System Architecture (HSA) Foundation
(msgpack)= [MsgPack] Message Pack
(opencl)= [OpenCL] The OpenCL Specification Version 2.0
(semver)= [SEMVER] Semantic Versioning
(yaml)= [YAML] YAML Ain't Markup Language (YAML™) Version 1.2