tree 0bae141b41421822fe3ade0a4e7ef3ada6538de2
parent 09810906cb64fbf60a6d5b5a637e9f859652bc80
author Craig Topper <craig.topper@sifive.com> 1618510106 -0700
committer Copybara-Service <copybara-worker@google.com> 1618603219 -0700

[RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.

This generalizes RVInstIShift/RVInstIShiftW to take the upper
5 or 7 bits of the immediate as an input instead of only bit 30. Then
we can share them.

For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets
a 7th bit for the shift amount.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100424

GitOrigin-RevId: 1656df13daa146afeb75ad832c94830a1f47d9cf