| commit | fe70c6903dbc601541f09528b4d02c8ea306320e | [log] [tgz] |
|---|---|---|
| author | Craig Topper <craig.topper@sifive.com> | Thu Apr 15 11:08:26 2021 -0700 |
| committer | Copybara-Service <copybara-worker@google.com> | Fri Apr 16 13:00:19 2021 -0700 |
| tree | 0bae141b41421822fe3ade0a4e7ef3ada6538de2 | |
| parent | 09810906cb64fbf60a6d5b5a637e9f859652bc80 [diff] |
[RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension. This generalizes RVInstIShift/RVInstIShiftW to take the upper 5 or 7 bits of the immediate as an input instead of only bit 30. Then we can share them. For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets a 7th bit for the shift amount. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D100424 GitOrigin-RevId: 1656df13daa146afeb75ad832c94830a1f47d9cf