tree 3aac308195ec8d78ffb44067093e60688db37ee1
parent 6b03ec73557b98bb87bfea9be97a50b9d55a4ac7
author Hsiangkai Wang <kai.wang@sifive.com> 1613631139 +0800
committer Copybara-Service <copybara-worker@google.com> 1613734225 -0800

[RISCV] Fix bugs in pseudo instructions for masked segment load.

For masked segment load, the destination register should not overlap
with mask register. It could not be V0.

In the original implementation, there is no segment load/store register
class without V0. In this patch, I added these register classes and
modify `GetVRegNoV0` to get the correct one.

Differential Revision: https://reviews.llvm.org/D96937

GitOrigin-RevId: f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece