test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv32 -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck -check-prefix=RV32I %s

---
name:            load_i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; RV32I-LABEL: name: load_i8
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
    ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %3:_(s32) = G_LOAD %0(p0) :: (load (s8))
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10

...
---
name:            load_i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; RV32I-LABEL: name: load_i16
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
    ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %3:_(s32) = G_LOAD %0(p0) :: (load (s16))
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10

...
---
name:            load_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; RV32I-LABEL: name: load_i32
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
    ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %3:_(s32) = G_LOAD %0(p0) :: (load (s32))
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10

...
---
name:            load_ptr
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; RV32I-LABEL: name: load_ptr
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0))
    ; RV32I-NEXT: $x10 = COPY [[LOAD]](p0)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %3:_(p0) = G_LOAD %0(p0) :: (load (p0))
    $x10 = COPY %3(p0)
    PseudoRET implicit $x10

...
---
name:            zextload_i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; RV32I-LABEL: name: zextload_i8
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
    ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...
---
name:            zextload_i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    ; RV32I-LABEL: name: zextload_i16
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
    ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...