test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv32 -mattr=+m -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck -check-prefix=RV32I %s

---
name:            add_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: add_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[ADD]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_ADD %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sub_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: sub_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SUB]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_SUB %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            shl_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: shl_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]](s32)
    ; RV32I-NEXT: $x10 = COPY [[SHL]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_SHL %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            ashr_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: ashr_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
    ; RV32I-NEXT: $x10 = COPY [[ASHR]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_ASHR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            lshr_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: lshr_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
    ; RV32I-NEXT: $x10 = COPY [[LSHR]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_LSHR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            and_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: and_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[AND]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_AND %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            or_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: or_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[OR]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_OR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            xor_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: xor_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[XOR]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_XOR %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            mul_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: mul_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[MUL]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_MUL %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            sdiv_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: sdiv_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SDIV]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_SDIV %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            srem_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: srem_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SREM]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_SREM %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            smulh_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: smulh_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[SMULH:%[0-9]+]]:gprb(s32) = G_SMULH [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[SMULH]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_SMULH %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            udiv_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: udiv_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[UDIV]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_UDIV %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            urem_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: urem_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[UREM]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_UREM %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            umulh_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: umulh_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[UMULH]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_UMULH %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            icmp_i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: icmp_i32
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_ICMP intpred(eq), %0(s32), %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            icmp_ptr
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: icmp_ptr
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
    ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
    ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %1:_(p0) = COPY $x11
    %2:_(s32) = G_ICMP intpred(eq), %0(p0), %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...
---
name:            gep
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: gep
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
    ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s32)
    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY [[PTR_ADD]](p0)
    ; RV32I-NEXT: $x10 = COPY [[COPY2]](p0)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(p0) = G_PTR_ADD %0, %1(s32)
    %3:_(p0) = COPY %2(p0)
    $x10 = COPY %3(p0)
    PseudoRET implicit $x10

...