| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ |
| # RUN: | FileCheck %s |
| |
| --- |
| name: load_i8 |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i8 |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) |
| ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %0:_(p0) = COPY $x10 |
| %1:_(s8) = G_LOAD %0(p0) :: (load (s8)) |
| %2:_(s32) = G_ANYEXT %1(s8) |
| $x10 = COPY %2(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: load_i16 |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i16 |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16)) |
| ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %0:_(p0) = COPY $x10 |
| %1:_(s16) = G_LOAD %0(p0) :: (load (s16)) |
| %2:_(s32) = G_ANYEXT %1(s16) |
| $x10 = COPY %2(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: load_i32 |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i32 |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) |
| ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %0:_(p0) = COPY $x10 |
| %1:_(s32) = G_LOAD %0(p0) :: (load (s32)) |
| $x10 = COPY %1(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: load_i64 |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| - { id: 3, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i64 |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32) |
| ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4) |
| ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) |
| ; CHECK-NEXT: $x11 = COPY [[LOAD1]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 |
| %0:_(p0) = COPY $x10 |
| %1:_(s64) = G_LOAD %0(p0) :: (load (s64)) |
| %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) |
| $x10 = COPY %2(s32) |
| $x11 = COPY %3(s32) |
| PseudoRET implicit $x10, implicit $x11 |
| |
| ... |
| --- |
| name: load_ptr |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_ptr |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0), align 8) |
| ; CHECK-NEXT: $x10 = COPY [[LOAD]](p0) |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %0:_(p0) = COPY $x10 |
| %1:_(p0) = G_LOAD %0(p0) :: (load (p0), align 8) |
| $x10 = COPY %1(p0) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: load_i16_unaligned |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i16_unaligned |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32) |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) |
| ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) |
| ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] |
| ; CHECK-NEXT: $x10 = COPY [[OR]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %0:_(p0) = COPY $x10 |
| %1:_(s16) = G_LOAD %0(p0) :: (load (s16), align 1) |
| %2:_(s32) = G_ANYEXT %1(s16) |
| $x10 = COPY %2(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: load_i32_unaligned |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i32_unaligned |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32) |
| ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) |
| ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD1]], [[C1]](s32) |
| ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] |
| ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s32) |
| ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) |
| ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C3]](s32) |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) |
| ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C4]](s32) |
| ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD2]] |
| ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C5]](s32) |
| ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]] |
| ; CHECK-NEXT: $x10 = COPY [[OR2]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %0:_(p0) = COPY $x10 |
| %1:_(s32) = G_LOAD %0(p0) :: (load (s32), align 1) |
| $x10 = COPY %1(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: load_i32_align2 |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i32_align2 |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32) |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) |
| ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) |
| ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] |
| ; CHECK-NEXT: $x10 = COPY [[OR]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10 |
| %0:_(p0) = COPY $x10 |
| %1:_(s32) = G_LOAD %0(p0) :: (load (s32), align 2) |
| $x10 = COPY %1(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: load_i64_unaligned |
| alignment: 4 |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| - { id: 3, class: _ } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: |
| varArgsFrameIndex: 0 |
| varArgsSaveSize: 0 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; CHECK-LABEL: name: load_i64_unaligned |
| ; CHECK: liveins: $x10 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 |
| ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32) |
| ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) |
| ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD1]], [[C1]](s32) |
| ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] |
| ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s32) |
| ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) |
| ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C3]](s32) |
| ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) |
| ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C4]](s32) |
| ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD2]] |
| ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C5]](s32) |
| ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]] |
| ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32) |
| ; CHECK-NEXT: [[ZEXTLOAD3:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD3]](p0) :: (load (s8) from unknown-address + 4) |
| ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C7]](s32) |
| ; CHECK-NEXT: [[ZEXTLOAD4:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5) |
| ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD4]], [[C8]](s32) |
| ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]] |
| ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C9]](s32) |
| ; CHECK-NEXT: [[ZEXTLOAD5:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6) |
| ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C10]](s32) |
| ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7) |
| ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LOAD1]], [[C11]](s32) |
| ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[ZEXTLOAD5]] |
| ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C12]](s32) |
| ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]] |
| ; CHECK-NEXT: $x10 = COPY [[OR2]](s32) |
| ; CHECK-NEXT: $x11 = COPY [[OR5]](s32) |
| ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 |
| %0:_(p0) = COPY $x10 |
| %1:_(s64) = G_LOAD %0(p0) :: (load (s64), align 1) |
| %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) |
| $x10 = COPY %2(s32) |
| $x11 = COPY %3(s32) |
| PseudoRET implicit $x10, implicit $x11 |
| |
| ... |