test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name:            sext_32_64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    ; CHECK-LABEL: name: sext_32_64
    ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 524288
    ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 0
    ; CHECK-NEXT: $x8 = COPY [[ADDIW]]
    %0:gprb(s32) = G_CONSTANT i32 -2147483648
    %1:gprb(s64) = G_SEXT %0
    $x8 = COPY %1(s64)
...
---
name:            sext_inreg_64_32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    ; CHECK-LABEL: name: sext_inreg_64_32
    ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 524288
    ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 0
    ; CHECK-NEXT: $x8 = COPY [[ADDIW]]
    %0:gprb(s64) = G_CONSTANT i64 -2147483648
    %1:gprb(s64) = G_SEXT_INREG %0, 32
    $x8 = COPY %1(s64)
...