test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s

---
name:            virt_to_phys
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:

    ; RV32I-LABEL: name: virt_to_phys
    ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; RV32I-NEXT: $x10 = COPY [[ADDI]]
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_CONSTANT i32 1
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            phys_to_phys
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; RV32I-LABEL: name: phys_to_phys
    ; RV32I: liveins: $x10, $x11
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: $x10 = COPY $x11
    ; RV32I-NEXT: PseudoRET implicit $x10
    $x10 = COPY $x11
    PseudoRET implicit $x10

...
---
name:            virt_to_virt
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:

    ; RV32I-LABEL: name: virt_to_virt
    ; RV32I: PseudoRET
    %0:gprb(s32) = G_CONSTANT i32 1
    %1:gprb(s32) = COPY %0(s32)
    PseudoRET

...
---
name:            phys_to_virt
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; RV32I-LABEL: name: phys_to_virt
    ; RV32I: liveins: $x10
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: PseudoRET
    %0:gprb(s32) = COPY $x10
    PseudoRET

...