# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s

--- |
  define dso_local <4 x i32> @exit_liveout(i16* nocapture readonly %a, i16* nocapture readonly %b, i32* %c, i32 %N, <4 x i32> %pass) {
  entry:
    %cmp9 = icmp eq i32 %N, 0
    %tmp = add i32 %N, 3
    %tmp1 = lshr i32 %tmp, 2
    %tmp2 = shl nuw i32 %tmp1, 2
    %tmp3 = add i32 %tmp2, -4
    %tmp4 = lshr i32 %tmp3, 2
    %tmp5 = add nuw nsw i32 %tmp4, 1
    br i1 %cmp9, label %exit, label %vector.ph

  vector.ph:                                        ; preds = %entry
    %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)
    br label %vector.body

  vector.body:                                      ; preds = %vector.body, %vector.ph
    %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
    %lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ]
    %lsr.iv20 = phi i32* [ %scevgep20, %vector.body ], [ %c, %vector.ph ]
    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]
    %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]
    %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>*
    %lsr.store = bitcast i32* %lsr.iv20 to <4 x i32>*
    %lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>*
    %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)
    %tmp9 = sub i32 %tmp7, 4
    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
    %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
    %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
    %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>
    %tmp12 = mul nsw <4 x i32> %tmp11, %tmp10
    %tmp13 = add <4 x i32> %tmp12, %vec.phi
    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp13, <4 x i32>* %lsr.store, i32 4, <4 x i1> %tmp8)
    %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
    %scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4
    %scevgep20 = getelementptr i32, i32* %lsr.iv20, i32 4
    %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
    %tmp15 = icmp ne i32 %tmp14, 0
    %lsr.iv.next = add nsw i32 %lsr.iv1, -1
    br i1 %tmp15, label %vector.body, label %exit

  exit:                                             ; preds = %vector.body, %entry
    ret <4 x i32> %pass
  }

  declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
  declare i32 @llvm.start.loop.iterations.i32(i32)
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
  declare <4 x i1> @llvm.arm.mve.vctp32(i32)

...
---
name:            exit_liveout
alignment:       2
tracksRegLiveness: true
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    8
fixedStack:
  - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,
      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: exit_liveout
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
  ; CHECK:   renamable $r12 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8)
  ; CHECK:   tCBZ $r3, %bb.3
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $q0, $r0, $r1, $r2, $r3
  ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $q1, $r0, $r1, $r2
  ; CHECK:   renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv17, align 2)
  ; CHECK:   renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.lsr.iv1820, align 2)
  ; CHECK:   renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
  ; CHECK:   renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
  ; CHECK:   renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg :: (store 16 into %ir.lsr.store, align 4)
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.exit:
  ; CHECK:   liveins: $q0
  ; CHECK:   renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
  bb.0.entry:
    successors: %bb.3(0x30000000), %bb.1(0x50000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $lr

    frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r4, -8
    renamable $r12 = t2ADDri $sp, 8, 14, $noreg, $noreg
    renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8)
    tCBZ $r3, %bb.3

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $q0, $r0, $r1, $r2, $r3

    renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
    renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
    renamable $r4 = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
    $lr = t2DoLoopStart renamable $r4
    $r12 = tMOVr killed $r4, 14, $noreg

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r12

    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
    renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
    $lr = tMOVr $r12, 14, $noreg
    renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
    renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
    renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
    renamable $lr = t2LoopDec killed renamable $lr, 1
    MVE_VPST 8, implicit $vpr
    renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.store, align 4)
    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14, $noreg

  bb.3.exit:
    liveins: $q0

    renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14, $noreg
    renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14, $noreg, implicit $q0
    tPOP_RET 14, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3

...