)]}'
{
  "commit": "b72b4128f221fd5086a1ae46aba7b2fcbf0d6384",
  "tree": "16c559f5f1136aa44f6eba0bf599393d0f1a8d82",
  "parents": [
    "672f2726fd1e1a6d40acccc4a036beb2f6d16602"
  ],
  "author": {
    "name": "Matt Arsenault",
    "email": "Matthew.Arsenault@amd.com",
    "time": "Tue Jul 25 18:35:28 2023 -0400"
  },
  "committer": {
    "name": "Copybara-Service",
    "email": "copybara-worker@google.com",
    "time": "Mon Oct 02 02:16:29 2023 -0700"
  },
  "message": "RegisterCoalescer: Forcibly leave SSA to avoid MIR test errors\n\nNot sure how to produce a test that demonstrates the problem\ntoday. The coalescer would have to introduce a verifier caught SSA\nviolation, like multiple defs of a virtual register. I\u0027m not sure what\nwould do that now, but an upcoming patch will.\n\nhttps://reviews.llvm.org/D156271\n\nGitOrigin-RevId: 32a23aecf8002e181eb1022b8733ef8666b3241f\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "238462113bfe78c9f75a7af4d6f48eddabdae4b4",
      "old_mode": 33188,
      "old_path": "lib/CodeGen/RegisterCoalescer.cpp",
      "new_id": "516095a699ea1e8c26afb0cdecac4da288941167",
      "new_mode": 33188,
      "new_path": "lib/CodeGen/RegisterCoalescer.cpp"
    }
  ]
}