| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| ; RUN: opt -passes=lower-matrix-intrinsics,instcombine -fuse-matrix-use-loops -fuse-matrix-tile-size=2 -matrix-allow-contract -force-fuse-matrix -verify-dom-info %s -S | FileCheck %s |
| |
| ; REQUIRES: aarch64-registered-target |
| |
| target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" |
| target triple = "aarch64-apple-ios" |
| |
| define void @multiply_noalias_4x4(ptr noalias %A, ptr noalias %B, ptr noalias %C) { |
| ; CHECK-LABEL: @multiply_noalias_4x4( |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br label [[COLS_HEADER:%.*]] |
| ; CHECK: cols.header: |
| ; CHECK-NEXT: [[COLS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[COLS_STEP:%.*]], [[COLS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[COLS_BODY:%.*]] |
| ; CHECK: cols.body: |
| ; CHECK-NEXT: br label [[ROWS_HEADER:%.*]] |
| ; CHECK: rows.header: |
| ; CHECK-NEXT: [[ROWS_IV:%.*]] = phi i64 [ 0, [[COLS_BODY]] ], [ [[ROWS_STEP:%.*]], [[ROWS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[ROWS_BODY:%.*]] |
| ; CHECK: rows.body: |
| ; CHECK-NEXT: br label [[INNER_HEADER:%.*]] |
| ; CHECK: inner.header: |
| ; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[ROWS_BODY]] ], [ [[INNER_STEP:%.*]], [[INNER_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_0:%.*]] = phi <2 x double> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP7:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_1:%.*]] = phi <2 x double> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP9:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: br label [[INNER_BODY:%.*]] |
| ; CHECK: inner.body: |
| ; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INNER_IV]], 2 |
| ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr double, ptr [[A:%.*]], i64 [[TMP1]] |
| ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[TMP2]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[TMP2]], i64 4 |
| ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 |
| ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B:%.*]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[TMP5]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[TMP5]], i64 4 |
| ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8 |
| ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP6:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD]], <2 x double> [[SPLAT_SPLAT]], <2 x double> [[RESULT_VEC_0]]) |
| ; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP7]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT8]], <2 x double> [[TMP6]]) |
| ; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP8:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD]], <2 x double> [[SPLAT_SPLAT12]], <2 x double> [[RESULT_VEC_1]]) |
| ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP9]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT15]], <2 x double> [[TMP8]]) |
| ; CHECK-NEXT: br label [[INNER_LATCH]] |
| ; CHECK: inner.latch: |
| ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 |
| ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_STEP]], 4 |
| ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: rows.latch: |
| ; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2 |
| ; CHECK-NEXT: [[ROWS_COND_NOT:%.*]] = icmp eq i64 [[ROWS_STEP]], 4 |
| ; CHECK-NEXT: [[TMP10:%.*]] = shl i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[C:%.*]], i64 [[TMP11]] |
| ; CHECK-NEXT: store <2 x double> [[TMP7]], ptr [[TMP12]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP16:%.*]] = getelementptr double, ptr [[TMP12]], i64 4 |
| ; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[VEC_GEP16]], align 8 |
| ; CHECK-NEXT: br i1 [[ROWS_COND_NOT]], label [[COLS_LATCH]], label [[ROWS_HEADER]] |
| ; CHECK: cols.latch: |
| ; CHECK-NEXT: [[COLS_STEP]] = add i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[COLS_COND_NOT:%.*]] = icmp eq i64 [[COLS_STEP]], 4 |
| ; CHECK-NEXT: br i1 [[COLS_COND_NOT]], label [[CONTINUE:%.*]], label [[COLS_HEADER]] |
| ; CHECK: continue: |
| ; CHECK-NEXT: ret void |
| ; |
| |
| entry: |
| %a = load <16 x double>, ptr %A, align 8 |
| %b = load <16 x double>, ptr %B, align 8 |
| |
| %c = call <16 x double> @llvm.matrix.multiply.v16f64.v16f64.v16f64(<16 x double> %a, <16 x double> %b, i32 4, i32 4, i32 4) |
| |
| store <16 x double> %c, ptr %C, align 8 |
| ret void |
| } |
| |
| |
| declare <16 x double> @llvm.matrix.multiply.v16f64.v16f64.v16f64(<16 x double>, <16 x double>, i32, i32, i32) |
| |
| define void @multiply_noalias_2x4(ptr noalias %A, ptr noalias %B, ptr noalias %C) { |
| ; CHECK-LABEL: @multiply_noalias_2x4( |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br label [[COLS_HEADER:%.*]] |
| ; CHECK: cols.header: |
| ; CHECK-NEXT: [[COLS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[COLS_STEP:%.*]], [[COLS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[COLS_BODY:%.*]] |
| ; CHECK: cols.body: |
| ; CHECK-NEXT: br label [[ROWS_HEADER:%.*]] |
| ; CHECK: rows.header: |
| ; CHECK-NEXT: [[ROWS_IV:%.*]] = phi i64 [ 0, [[COLS_BODY]] ], [ [[ROWS_STEP:%.*]], [[ROWS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[ROWS_BODY:%.*]] |
| ; CHECK: rows.body: |
| ; CHECK-NEXT: br label [[INNER_HEADER:%.*]] |
| ; CHECK: inner.header: |
| ; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[ROWS_BODY]] ], [ [[INNER_STEP:%.*]], [[INNER_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_0:%.*]] = phi <2 x i64> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP9:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_1:%.*]] = phi <2 x i64> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP13:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: br label [[INNER_BODY:%.*]] |
| ; CHECK: inner.body: |
| ; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INNER_IV]], 1 |
| ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A:%.*]], i64 [[TMP1]] |
| ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr i64, ptr [[TMP2]], i64 2 |
| ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x i64>, ptr [[VEC_GEP]], align 8 |
| ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[B:%.*]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr i64, ptr [[TMP5]], i64 4 |
| ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x i64>, ptr [[VEC_GEP3]], align 8 |
| ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[RESULT_VEC_0]], [[TMP6]] |
| ; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP8:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT8]] |
| ; CHECK-NEXT: [[TMP9]] = add <2 x i64> [[TMP7]], [[TMP8]] |
| ; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT12]] |
| ; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[RESULT_VEC_1]], [[TMP10]] |
| ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT15]] |
| ; CHECK-NEXT: [[TMP13]] = add <2 x i64> [[TMP11]], [[TMP12]] |
| ; CHECK-NEXT: br label [[INNER_LATCH]] |
| ; CHECK: inner.latch: |
| ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 |
| ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_STEP]], 4 |
| ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP2:![0-9]+]] |
| ; CHECK: rows.latch: |
| ; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2 |
| ; CHECK-NEXT: [[ROWS_COND_NOT:%.*]] = icmp eq i64 [[ROWS_IV]], 0 |
| ; CHECK-NEXT: [[TMP14:%.*]] = shl i64 [[COLS_IV]], 1 |
| ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[C:%.*]], i64 [[TMP15]] |
| ; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr [[TMP16]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP16:%.*]] = getelementptr i64, ptr [[TMP16]], i64 2 |
| ; CHECK-NEXT: store <2 x i64> [[TMP13]], ptr [[VEC_GEP16]], align 8 |
| ; CHECK-NEXT: br i1 [[ROWS_COND_NOT]], label [[COLS_LATCH]], label [[ROWS_HEADER]] |
| ; CHECK: cols.latch: |
| ; CHECK-NEXT: [[COLS_STEP]] = add i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[COLS_COND_NOT:%.*]] = icmp eq i64 [[COLS_IV]], 0 |
| ; CHECK-NEXT: br i1 [[COLS_COND_NOT]], label [[CONTINUE:%.*]], label [[COLS_HEADER]] |
| ; CHECK: continue: |
| ; CHECK-NEXT: ret void |
| ; |
| |
| ; In the inner loop, compute |
| ; Result += Load(A, ROWS_IV, INNER_IV) * Load(B, INNER_IV, COLS_IV) |
| |
| |
| ; Store the current 2x2 tile. |
| |
| entry: |
| %a = load <8 x i64>, ptr %A, align 8 |
| %b = load <8 x i64>, ptr %B, align 8 |
| |
| %c = call <4 x i64> @llvm.matrix.multiply.v4i64.v8i64.v8i64(<8 x i64> %a, <8 x i64> %b, i32 2, i32 4, i32 2) |
| |
| store <4 x i64> %c, ptr %C, align 8 |
| ret void |
| } |
| |
| |
| declare <4 x i64> @llvm.matrix.multiply.v4i64.v8i64.v8i64(<8 x i64>, <8 x i64>, i32, i32, i32) |
| |
| define void @multiply_noalias_4x2_2x8(ptr noalias %A, ptr noalias %B, ptr noalias %C) { |
| ; CHECK-LABEL: @multiply_noalias_4x2_2x8( |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br label [[COLS_HEADER:%.*]] |
| ; CHECK: cols.header: |
| ; CHECK-NEXT: [[COLS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[COLS_STEP:%.*]], [[COLS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[COLS_BODY:%.*]] |
| ; CHECK: cols.body: |
| ; CHECK-NEXT: br label [[ROWS_HEADER:%.*]] |
| ; CHECK: rows.header: |
| ; CHECK-NEXT: [[ROWS_IV:%.*]] = phi i64 [ 0, [[COLS_BODY]] ], [ [[ROWS_STEP:%.*]], [[ROWS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[ROWS_BODY:%.*]] |
| ; CHECK: rows.body: |
| ; CHECK-NEXT: br label [[INNER_HEADER:%.*]] |
| ; CHECK: inner.header: |
| ; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[ROWS_BODY]] ], [ [[INNER_STEP:%.*]], [[INNER_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_0:%.*]] = phi <2 x i64> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP9:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_1:%.*]] = phi <2 x i64> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP13:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: br label [[INNER_BODY:%.*]] |
| ; CHECK: inner.body: |
| ; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INNER_IV]], 2 |
| ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A:%.*]], i64 [[TMP1]] |
| ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr i64, ptr [[TMP2]], i64 4 |
| ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x i64>, ptr [[VEC_GEP]], align 8 |
| ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[COLS_IV]], 1 |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[B:%.*]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr i64, ptr [[TMP5]], i64 2 |
| ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x i64>, ptr [[VEC_GEP3]], align 8 |
| ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[RESULT_VEC_0]], [[TMP6]] |
| ; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP8:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT8]] |
| ; CHECK-NEXT: [[TMP9]] = add <2 x i64> [[TMP7]], [[TMP8]] |
| ; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT12]] |
| ; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[RESULT_VEC_1]], [[TMP10]] |
| ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT15]] |
| ; CHECK-NEXT: [[TMP13]] = add <2 x i64> [[TMP11]], [[TMP12]] |
| ; CHECK-NEXT: br label [[INNER_LATCH]] |
| ; CHECK: inner.latch: |
| ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 |
| ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_IV]], 0 |
| ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: rows.latch: |
| ; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2 |
| ; CHECK-NEXT: [[ROWS_COND_NOT:%.*]] = icmp eq i64 [[ROWS_STEP]], 4 |
| ; CHECK-NEXT: [[TMP14:%.*]] = shl i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[C:%.*]], i64 [[TMP15]] |
| ; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr [[TMP16]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP16:%.*]] = getelementptr i64, ptr [[TMP16]], i64 4 |
| ; CHECK-NEXT: store <2 x i64> [[TMP13]], ptr [[VEC_GEP16]], align 8 |
| ; CHECK-NEXT: br i1 [[ROWS_COND_NOT]], label [[COLS_LATCH]], label [[ROWS_HEADER]] |
| ; CHECK: cols.latch: |
| ; CHECK-NEXT: [[COLS_STEP]] = add i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[COLS_COND_NOT:%.*]] = icmp eq i64 [[COLS_STEP]], 8 |
| ; CHECK-NEXT: br i1 [[COLS_COND_NOT]], label [[CONTINUE:%.*]], label [[COLS_HEADER]] |
| ; CHECK: continue: |
| ; CHECK-NEXT: ret void |
| ; |
| |
| ; In the inner loop, compute |
| ; Result += Load(A, ROWS_IV, INNER_IV) * Load(B, INNER_IV, COLS_IV) |
| |
| |
| ; Store the current 2x2 tile. |
| |
| entry: |
| %a = load <8 x i64>, ptr %A, align 8 |
| %b = load <16 x i64>, ptr %B, align 8 |
| |
| %c = call <32 x i64> @llvm.matrix.multiply.v32i64.v8i64.v16i64(<8 x i64> %a, <16 x i64> %b, i32 4, i32 2, i32 8) |
| |
| store <32 x i64> %c, ptr %C, align 8 |
| ret void |
| } |
| |
| declare <32 x i64> @llvm.matrix.multiply.v32i64.v8i64.v16i64(<8 x i64>, <16 x i64>, i32, i32, i32) |
| |
| |
| ; Check the runtime aliasing checks. |
| define void @multiply_alias_2x2(ptr %A, ptr %B, ptr %C) { |
| ; CHECK-LABEL: @multiply_alias_2x2( |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[STORE_BEGIN:%.*]] = ptrtoint ptr [[C:%.*]] to i64 |
| ; CHECK-NEXT: [[STORE_END:%.*]] = add nuw nsw i64 [[STORE_BEGIN]], 16 |
| ; CHECK-NEXT: [[LOAD_BEGIN:%.*]] = ptrtoint ptr [[A:%.*]] to i64 |
| ; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[STORE_END]], [[LOAD_BEGIN]] |
| ; CHECK-NEXT: br i1 [[TMP0]], label [[ALIAS_CONT:%.*]], label [[NO_ALIAS:%.*]] |
| ; CHECK: alias_cont: |
| ; CHECK-NEXT: [[LOAD_END:%.*]] = add nuw nsw i64 [[LOAD_BEGIN]], 16 |
| ; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[LOAD_END]], [[STORE_BEGIN]] |
| ; CHECK-NEXT: br i1 [[TMP1]], label [[COPY:%.*]], label [[NO_ALIAS]] |
| ; CHECK: copy: |
| ; CHECK-NEXT: [[TMP2:%.*]] = alloca [4 x float], align 4 |
| ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) [[TMP2]], ptr noundef nonnull align 8 dereferenceable(16) [[A]], i64 16, i1 false) |
| ; CHECK-NEXT: br label [[NO_ALIAS]] |
| ; CHECK: no_alias: |
| ; CHECK-NEXT: [[TMP3:%.*]] = phi ptr [ [[A]], [[ENTRY:%.*]] ], [ [[A]], [[ALIAS_CONT]] ], [ [[TMP2]], [[COPY]] ] |
| ; CHECK-NEXT: [[STORE_BEGIN4:%.*]] = ptrtoint ptr [[C]] to i64 |
| ; CHECK-NEXT: [[STORE_END5:%.*]] = add nuw nsw i64 [[STORE_BEGIN4]], 16 |
| ; CHECK-NEXT: [[LOAD_BEGIN6:%.*]] = ptrtoint ptr [[B:%.*]] to i64 |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i64 [[STORE_END5]], [[LOAD_BEGIN6]] |
| ; CHECK-NEXT: br i1 [[TMP4]], label [[ALIAS_CONT1:%.*]], label [[NO_ALIAS3:%.*]] |
| ; CHECK: alias_cont1: |
| ; CHECK-NEXT: [[LOAD_END7:%.*]] = add nuw nsw i64 [[LOAD_BEGIN6]], 16 |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[LOAD_END7]], [[STORE_BEGIN4]] |
| ; CHECK-NEXT: br i1 [[TMP5]], label [[COPY2:%.*]], label [[NO_ALIAS3]] |
| ; CHECK: copy2: |
| ; CHECK-NEXT: [[TMP6:%.*]] = alloca [4 x float], align 4 |
| ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) [[TMP6]], ptr noundef nonnull align 8 dereferenceable(16) [[B]], i64 16, i1 false) |
| ; CHECK-NEXT: br label [[NO_ALIAS3]] |
| ; CHECK: no_alias3: |
| ; CHECK-NEXT: [[TMP7:%.*]] = phi ptr [ [[B]], [[NO_ALIAS]] ], [ [[B]], [[ALIAS_CONT1]] ], [ [[TMP6]], [[COPY2]] ] |
| ; CHECK-NEXT: br label [[COLS_HEADER:%.*]] |
| ; CHECK: cols.header: |
| ; CHECK-NEXT: [[COLS_IV:%.*]] = phi i64 [ 0, [[NO_ALIAS3]] ], [ [[COLS_STEP:%.*]], [[COLS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[COLS_BODY:%.*]] |
| ; CHECK: cols.body: |
| ; CHECK-NEXT: br label [[ROWS_HEADER:%.*]] |
| ; CHECK: rows.header: |
| ; CHECK-NEXT: [[ROWS_IV:%.*]] = phi i64 [ 0, [[COLS_BODY]] ], [ [[ROWS_STEP:%.*]], [[ROWS_LATCH:%.*]] ] |
| ; CHECK-NEXT: br label [[ROWS_BODY:%.*]] |
| ; CHECK: rows.body: |
| ; CHECK-NEXT: br label [[INNER_HEADER:%.*]] |
| ; CHECK: inner.header: |
| ; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[ROWS_BODY]] ], [ [[INNER_STEP:%.*]], [[INNER_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_0:%.*]] = phi <2 x float> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP15:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: [[RESULT_VEC_1:%.*]] = phi <2 x float> [ zeroinitializer, [[ROWS_BODY]] ], [ [[TMP17:%.*]], [[INNER_LATCH]] ] |
| ; CHECK-NEXT: br label [[INNER_BODY:%.*]] |
| ; CHECK: inner.body: |
| ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[INNER_IV]], 1 |
| ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr float, ptr [[TMP3]], i64 [[TMP9]] |
| ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x float>, ptr [[TMP10]], align 4 |
| ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr float, ptr [[TMP10]], i64 2 |
| ; CHECK-NEXT: [[COL_LOAD8:%.*]] = load <2 x float>, ptr [[VEC_GEP]], align 4 |
| ; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[COLS_IV]], 1 |
| ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], [[INNER_IV]] |
| ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr float, ptr [[TMP7]], i64 [[TMP12]] |
| ; CHECK-NEXT: [[COL_LOAD9:%.*]] = load <2 x float>, ptr [[TMP13]], align 4 |
| ; CHECK-NEXT: [[VEC_GEP10:%.*]] = getelementptr float, ptr [[TMP13]], i64 2 |
| ; CHECK-NEXT: [[COL_LOAD11:%.*]] = load <2 x float>, ptr [[VEC_GEP10]], align 4 |
| ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x float> [[COL_LOAD9]], <2 x float> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD]], <2 x float> [[SPLAT_SPLAT]], <2 x float> [[RESULT_VEC_0]]) |
| ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x float> [[COL_LOAD9]], <2 x float> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP15]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD8]], <2 x float> [[SPLAT_SPLAT15]], <2 x float> [[TMP14]]) |
| ; CHECK-NEXT: [[SPLAT_SPLAT19:%.*]] = shufflevector <2 x float> [[COL_LOAD11]], <2 x float> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP16:%.*]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD]], <2 x float> [[SPLAT_SPLAT19]], <2 x float> [[RESULT_VEC_1]]) |
| ; CHECK-NEXT: [[SPLAT_SPLAT22:%.*]] = shufflevector <2 x float> [[COL_LOAD11]], <2 x float> undef, <2 x i32> <i32 1, i32 1> |
| ; CHECK-NEXT: [[TMP17]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD8]], <2 x float> [[SPLAT_SPLAT22]], <2 x float> [[TMP16]]) |
| ; CHECK-NEXT: br label [[INNER_LATCH]] |
| ; CHECK: inner.latch: |
| ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 |
| ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_IV]], 0 |
| ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; CHECK: rows.latch: |
| ; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2 |
| ; CHECK-NEXT: [[ROWS_COND_NOT:%.*]] = icmp eq i64 [[ROWS_IV]], 0 |
| ; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[COLS_IV]], 1 |
| ; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[TMP18]], [[ROWS_IV]] |
| ; CHECK-NEXT: [[TMP20:%.*]] = getelementptr float, ptr [[C]], i64 [[TMP19]] |
| ; CHECK-NEXT: store <2 x float> [[TMP15]], ptr [[TMP20]], align 8 |
| ; CHECK-NEXT: [[VEC_GEP23:%.*]] = getelementptr float, ptr [[TMP20]], i64 2 |
| ; CHECK-NEXT: store <2 x float> [[TMP17]], ptr [[VEC_GEP23]], align 8 |
| ; CHECK-NEXT: br i1 [[ROWS_COND_NOT]], label [[COLS_LATCH]], label [[ROWS_HEADER]] |
| ; CHECK: cols.latch: |
| ; CHECK-NEXT: [[COLS_STEP]] = add i64 [[COLS_IV]], 2 |
| ; CHECK-NEXT: [[COLS_COND_NOT:%.*]] = icmp eq i64 [[COLS_IV]], 0 |
| ; CHECK-NEXT: br i1 [[COLS_COND_NOT]], label [[CONTINUE:%.*]], label [[COLS_HEADER]] |
| ; CHECK: continue: |
| ; CHECK-NEXT: ret void |
| ; |
| |
| ; First, check for aliasing at runtime, create non-aliasing copies if required. |
| entry: |
| %a = load <4 x float>, ptr %A, align 8 |
| %b = load <4 x float>, ptr %B, align 8 |
| |
| %c = call <4 x float> @llvm.matrix.multiply.v4f32.v4f32.v4f32(<4 x float> %a, <4 x float> %b, i32 2, i32 2, i32 2) |
| |
| store <4 x float> %c, ptr %C, align 8 |
| ret void |
| } |
| |
| declare <4 x float> @llvm.matrix.multiply.v4f32.v4f32.v4f32(<4 x float>, <4 x float>, i32, i32, i32) |
| |
| ; CHECK: !0 = distinct !{!0, !1} |
| ; CHECK-NEXT: !1 = !{!"llvm.loop.unroll.count", i32 2} |
| ; CHECK-NEXT: !2 = distinct !{!2, !1} |
| ; CHECK-NEXT: !3 = distinct !{!3, !4} |
| ; CHECK-NEXT: !4 = !{!"llvm.loop.unroll.count", i32 1} |
| ; CHECK-NEXT: !5 = distinct !{!5, !4} |
