[RISCV] Remove redundant test cases for index segment load (4/8).

GitOrigin-RevId: 3b4b1c845a4b5e329065f59cb87dce7f528a16fd
diff --git a/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll b/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
index d2ca2f5..ee1979c 100644
--- a/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
+++ b/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
@@ -18,92 +18,20 @@
   ret <vscale x 16 x i16> %1
 }
 
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
+; CHECK-NEXT:    vmv4r.v v4, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
+; CHECK-NEXT:    vluxseg2ei16.v v4, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
   ret <vscale x 16 x i16> %1
 }
 
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v16, (a0), v8
-; CHECK-NEXT:    vmv4r.v v20, v16
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v20
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
 declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
 declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -120,534 +48,20 @@
   ret <vscale x 16 x i16> %1
 }
 
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
+; CHECK-NEXT:    vmv4r.v v4, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
+; CHECK-NEXT:    vluxseg2ei8.v v4, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
   ret <vscale x 16 x i16> %1
 }
 
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v16, (a0), v8
-; CHECK-NEXT:    vmv4r.v v20, v16
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v20
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v16, (a0), v8
-; CHECK-NEXT:    vmv4r.v v20, v16
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v20
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
 declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
 declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -664,160 +78,20 @@
   ret <vscale x 16 x i16> %1
 }
 
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v16, (a0), v8
-; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vmv4r.v v4, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v20
+; CHECK-NEXT:    vluxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
   ret <vscale x 16 x i16> %1
 }
 
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
-declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i16> @test_vluxseg2_nxv16i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv4r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
-  ret <vscale x 16 x i16> %1
-}
-
-define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v12, (a0), v8
-; CHECK-NEXT:    vmv4r.v v16, v12
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv4r.v v8, v16
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
-  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
-  ret <vscale x 16 x i16> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
@@ -834,160 +108,20 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg2ei32.v v6, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
@@ -1004,126 +138,20 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg2ei8.v v6, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
@@ -1140,58 +168,20 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg2ei64.v v6, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
@@ -1208,366 +198,20 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg2ei16.v v6, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg2_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg2_mask_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
@@ -1584,165 +228,22 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
+; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v4
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
@@ -1759,130 +260,22 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
+; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v4
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
@@ -1899,60 +292,21 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
+; CHECK-NEXT:    vmv2r.v v10, v6
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg3ei64.v v6, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
@@ -1969,377 +323,22 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
+; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v4
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg3_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg3_mask_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v12, (a0), v8
-; CHECK-NEXT:    vmv2r.v v14, v12
-; CHECK-NEXT:    vmv2r.v v16, v12
-; CHECK-NEXT:    vmv2r.v v18, v12
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v14
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v16, (a0), v8
-; CHECK-NEXT:    vmv2r.v v18, v16
-; CHECK-NEXT:    vmv2r.v v20, v16
-; CHECK-NEXT:    vmv2r.v v22, v16
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v18
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
@@ -2356,170 +355,23 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v12
+; CHECK-NEXT:    vmv2r.v v16, v12
+; CHECK-NEXT:    vmv2r.v v18, v12
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
+; CHECK-NEXT:    vluxseg4ei32.v v12, (a0), v10, v0.t
+; CHECK-NEXT:    vmv2r.v v8, v14
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
@@ -2536,134 +388,23 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v12
+; CHECK-NEXT:    vmv2r.v v16, v12
+; CHECK-NEXT:    vmv2r.v v18, v12
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
+; CHECK-NEXT:    vluxseg4ei8.v v12, (a0), v10, v0.t
+; CHECK-NEXT:    vmv2r.v v8, v14
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
@@ -2680,60 +421,21 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v12, (a0), v8
-; CHECK-NEXT:    vmv2r.v v14, v12
-; CHECK-NEXT:    vmv2r.v v16, v12
-; CHECK-NEXT:    vmv2r.v v18, v12
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v14
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv2r.v v16, v8
 ; CHECK-NEXT:    vmv2r.v v18, v16
 ; CHECK-NEXT:    vmv2r.v v20, v16
 ; CHECK-NEXT:    vmv2r.v v22, v16
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei64.v v16, (a0), v12, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v18
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
 }
 
 declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
@@ -2752,314 +454,23 @@
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v16, (a0), v8
-; CHECK-NEXT:    vmv2r.v v18, v16
-; CHECK-NEXT:    vmv2r.v v20, v16
-; CHECK-NEXT:    vmv2r.v v22, v16
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v18
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v12, (a0), v8
+; CHECK-NEXT:    vmv2r.v v12, v8
 ; CHECK-NEXT:    vmv2r.v v14, v12
 ; CHECK-NEXT:    vmv2r.v v16, v12
 ; CHECK-NEXT:    vmv2r.v v18, v12
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v12, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei16.v v12, (a0), v10, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v14
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
   ret <vscale x 4 x i32> %1
 }
 
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv2r.v v14, v12
-; CHECK-NEXT:    vmv2r.v v16, v12
-; CHECK-NEXT:    vmv2r.v v18, v12
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v14
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v16, (a0), v8
-; CHECK-NEXT:    vmv2r.v v18, v16
-; CHECK-NEXT:    vmv2r.v v20, v16
-; CHECK-NEXT:    vmv2r.v v22, v16
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v18
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
-declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define <vscale x 4 x i32> @test_vluxseg4_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
-  ret <vscale x 4 x i32> %1
-}
-
-define <vscale x 4 x i32> @test_vluxseg4_mask_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
-  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vluxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
-  ret <vscale x 4 x i32> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
@@ -3076,92 +487,20 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg2ei16.v v6, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -3178,534 +517,20 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg2ei8.v v6, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -3722,92 +547,20 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg2ei32.v v6, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg2_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg2_mask_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
@@ -3824,95 +577,21 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
+; CHECK-NEXT:    vmv2r.v v10, v6
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg3ei16.v v6, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -3929,550 +608,22 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
+; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v4
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -4489,95 +640,21 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v6, v8
+; CHECK-NEXT:    vmv2r.v v10, v6
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
+; CHECK-NEXT:    vluxseg3ei32.v v6, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg3_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg3_mask_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v2, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v4
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
@@ -4594,98 +671,23 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v12, (a0), v8
-; CHECK-NEXT:    vmv2r.v v14, v12
-; CHECK-NEXT:    vmv2r.v v16, v12
-; CHECK-NEXT:    vmv2r.v v18, v12
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v14
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv2r.v v16, v8
 ; CHECK-NEXT:    vmv2r.v v18, v16
 ; CHECK-NEXT:    vmv2r.v v20, v16
 ; CHECK-NEXT:    vmv2r.v v22, v16
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei16.v v16, (a0), v12, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v18
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -4702,566 +704,23 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v12, (a0), v8
+; CHECK-NEXT:    vmv2r.v v12, v8
 ; CHECK-NEXT:    vmv2r.v v14, v12
 ; CHECK-NEXT:    vmv2r.v v16, v12
 ; CHECK-NEXT:    vmv2r.v v18, v12
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v12, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei8.v v12, (a0), v10, v0.t
 ; CHECK-NEXT:    vmv2r.v v8, v14
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v16, (a0), v8
-; CHECK-NEXT:    vmv2r.v v18, v16
-; CHECK-NEXT:    vmv2r.v v20, v16
-; CHECK-NEXT:    vmv2r.v v22, v16
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v18
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v16, (a0), v8
-; CHECK-NEXT:    vmv2r.v v18, v16
-; CHECK-NEXT:    vmv2r.v v20, v16
-; CHECK-NEXT:    vmv2r.v v22, v16
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v18
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v12, (a0), v8
-; CHECK-NEXT:    vmv2r.v v14, v12
-; CHECK-NEXT:    vmv2r.v v16, v12
-; CHECK-NEXT:    vmv2r.v v18, v12
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v14
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v12, (a0), v8
-; CHECK-NEXT:    vmv2r.v v14, v12
-; CHECK-NEXT:    vmv2r.v v16, v12
-; CHECK-NEXT:    vmv2r.v v18, v12
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v12, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v14
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
 declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -5278,234 +737,22 @@
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v16, (a0), v8
-; CHECK-NEXT:    vmv2r.v v18, v16
-; CHECK-NEXT:    vmv2r.v v20, v16
-; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vmv2r.v v6, v8
+; CHECK-NEXT:    vmv2r.v v10, v6
+; CHECK-NEXT:    vmv2r.v v12, v6
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v16, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v18
+; CHECK-NEXT:    vluxseg4ei32.v v6, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
   ret <vscale x 16 x i8> %1
 }
 
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
-declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define <vscale x 16 x i8> @test_vluxseg4_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
-  ret <vscale x 16 x i8> %1
-}
-
-define <vscale x 16 x i8> @test_vluxseg4_mask_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8
-; CHECK-NEXT:    vmv2r.v v12, v10
-; CHECK-NEXT:    vmv2r.v v14, v10
-; CHECK-NEXT:    vmv2r.v v16, v10
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v10, (a0), v8, v0.t
-; CHECK-NEXT:    vmv2r.v v8, v12
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
-  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vluxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
-  ret <vscale x 16 x i8> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -5522,22 +769,18 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v7, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
+; CHECK-NEXT:    vluxseg2ei64.v v7, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v7_v8
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
 }
 
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
@@ -5556,92 +799,20 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v7, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
+; CHECK-NEXT:    vluxseg2ei32.v v7, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v7_v8
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -5658,228 +829,20 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v7, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
+; CHECK-NEXT:    vluxseg2ei16.v v7, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v7_v8
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -5896,368 +859,20 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v7, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
+; CHECK-NEXT:    vluxseg2ei8.v v7, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v7_v8
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg2_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg2_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg2_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg2_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg2ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -6274,23 +889,20 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
 }
 
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
@@ -6309,95 +921,22 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -6414,235 +953,22 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -6659,379 +985,22 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg3_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg3_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg3_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg3_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg3ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -7048,24 +1017,21 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
 }
 
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
@@ -7084,98 +1050,23 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -7192,242 +1083,23 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -7444,390 +1116,23 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg4_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg4_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg4_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg4_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg4ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -7844,25 +1149,22 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
 }
 
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
@@ -7881,101 +1183,24 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -7992,249 +1217,24 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -8251,401 +1251,24 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg5_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg5_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg5_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg5_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg5ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -8662,26 +1285,23 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
 }
 
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
@@ -8700,104 +1320,25 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -8814,256 +1355,25 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -9080,412 +1390,25 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg6_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg6_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg6_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg6_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg6ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -9502,11 +1425,10 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei64.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
@@ -9514,15 +1436,13 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei64.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
 }
 
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
@@ -9541,11 +1461,10 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei32.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
@@ -9553,95 +1472,15 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei32.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -9658,11 +1497,10 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
@@ -9670,251 +1508,15 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei32.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei32.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei32.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei16.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei64.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
-  ret <vscale x 1 x i64> %1
-}
-
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei64.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei64.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
 declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -9931,11 +1533,10 @@
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8
+; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
@@ -9943,411 +1544,15 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8, v0.t
+; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v2
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
-  ret <vscale x 1 x i64> %3
-}
-
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
-declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define <vscale x 1 x i64> @test_vluxseg7_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vluxseg7_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v0, (a0), v8
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
   ret <vscale x 1 x i64> %1
 }
 
-define <vscale x 1 x i64> @test_vluxseg7_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
-; CHECK-LABEL: test_vluxseg7_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
-; CHECK-NEXT:    vluxseg7ei8.v v1, (a0), v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v2
-; CHECK-NEXT:    ret
-entry:
-  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
-  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vluxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)