[RISCV] Remove redundant test cases for index segment store (8/8).

Differential Revision: https://reviews.llvm.org/D97026

GitOrigin-RevId: 0ab3558b25d6ba0b4606d3831c9bb1d98c17d113
diff --git a/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll b/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
index 04fe0bc..b8414bf 100644
--- a/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+++ b/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
@@ -33,66 +33,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -124,467 +64,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv8i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -614,126 +93,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv2i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
@@ -765,130 +124,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
@@ -920,99 +155,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
@@ -1042,35 +184,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
@@ -1102,308 +215,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
@@ -1435,130 +246,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
@@ -1590,99 +277,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
@@ -1714,37 +308,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
@@ -1776,320 +339,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
@@ -2123,138 +372,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
@@ -2288,105 +405,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
@@ -2420,39 +438,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
@@ -2486,270 +471,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
@@ -2779,66 +500,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -2870,461 +531,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -3354,68 +560,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
@@ -3447,68 +591,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -3540,471 +622,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -4036,68 +653,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
@@ -4131,72 +686,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -4230,501 +719,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
@@ -4758,188 +752,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -5002,66 +814,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -5093,186 +845,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -5304,308 +876,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -5668,68 +938,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -5761,192 +969,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -5978,324 +1000,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -6362,72 +1066,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -6461,204 +1099,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -6692,344 +1132,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -7100,76 +1202,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -7205,216 +1237,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -7450,364 +1272,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -7882,80 +1346,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -7993,228 +1383,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -8252,384 +1420,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -8708,84 +1498,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -8825,240 +1537,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -9098,404 +1576,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -9578,88 +1658,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -9701,252 +1699,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -9988,368 +1740,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -10412,66 +1802,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -10503,186 +1833,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -10714,308 +1864,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -11078,68 +1926,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -11171,192 +1957,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -11388,324 +1988,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -11772,72 +2054,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -11871,204 +2087,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -12102,344 +2120,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -12510,76 +2190,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
 declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
@@ -12615,216 +2225,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
 declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
@@ -12860,364 +2260,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
 declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
@@ -13292,80 +2334,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x