test/CodeGen/Thumb2/m4-sched-ldr.mir

# RUN: llc %s -run-pass machine-scheduler -o - | FileCheck %s

# CHECK-LABEL: bb.0.
# CHECK: t2LDRi12
# CHECK-NEXT: t2LDRi12
# CHECK-NEXT: t2ADDri
# CHECK-NEXT: t2ADDri
--- |
  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv7em-arm-none-eabi"

  ; Function Attrs: norecurse nounwind optsize readonly
  define dso_local i32 @test(i32* nocapture readonly %a, i32* nocapture readonly %b) local_unnamed_addr #0 {
  entry:
    %0 = load i32, i32* %a, align 4
    %add = add nsw i32 %0, 10
    %1 = load i32, i32* %b, align 4
    %add1 = add nsw i32 %1, 20
    %mul = mul nsw i32 %add1, %add
    ret i32 %mul
  }

  attributes #0 = { "target-cpu"="cortex-m4" }

...
---
name:            test
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gprnopc, preferred-register: '' }
  - { id: 3, class: rgpr, preferred-register: '' }
  - { id: 4, class: gprnopc, preferred-register: '' }
  - { id: 5, class: rgpr, preferred-register: '' }
  - { id: 6, class: rgpr, preferred-register: '' }
liveins:
  - { reg: '$r0', virtual-reg: '%0' }
  - { reg: '$r1', virtual-reg: '%1' }
body:             |
  bb.0.entry:
    liveins: $r0, $r1

    %1:gpr = COPY $r1
    %0:gpr = COPY $r0
    %2:gprnopc = t2LDRi12 %0, 0, 14, $noreg :: (load 4 from %ir.a)
    %3:rgpr = nsw t2ADDri %2, 10, 14, $noreg, $noreg
    %4:gprnopc = t2LDRi12 %1, 0, 14, $noreg :: (load 4 from %ir.b)
    %5:rgpr = nsw t2ADDri %4, 20, 14, $noreg, $noreg
    %6:rgpr = nsw t2MUL %5, %3, 14, $noreg
    $r0 = COPY %6
    tBX_RET 14, $noreg, implicit $r0

...