test/CodeGen/Thumb2/ifcvt-dead-predicate.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -run-pass=if-converter -simplify-mir | FileCheck %s

--- |
  ; ModuleID = 'ifcvt-dead-predicate.ll'
  source_filename = "ifcvt-dead-predicate.ll"
  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv7-unknown-linux-android16"

  ; Function Attrs: minsize nounwind optsize ssp uwtable
  define hidden zeroext i1 @branch_entry(i32* %command_set, i8* %requested_filename, i8** %filename_to_use) local_unnamed_addr #0 {
  entry:
    %0 = load i32, i32* %command_set, align 4
    %and.i.i = and i32 %0, 128
    %tobool.i.i.not = icmp eq i32 %and.i.i, 0
    br i1 %tobool.i.i.not, label %land.end, label %land.rhs

  land.rhs:                                         ; preds = %entry
    %call1 = tail call zeroext i1 @branch_target(i8* %requested_filename, i8** %filename_to_use)
    ret i1 %call1

  land.end:                                         ; preds = %entry
    ret i1 false
  }

  ; Function Attrs: minsize optsize
  declare zeroext i1 @branch_target(i8*, i8**) local_unnamed_addr #1

  attributes #0 = { minsize nounwind optsize ssp uwtable }
  attributes #1 = { minsize optsize }

...
---
name:            branch_entry
alignment:       2
tracksRegLiveness: true
liveins:
  - { reg: '$r0' }
  - { reg: '$r1' }
  - { reg: '$r2' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: branch_entry
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $r0 = tLDRBi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.command_set, align 4)
  ; CHECK:   dead renamable $r0, $cpsr = tLSLri killed renamable $r0, 24, 14 /* CC::al */, $noreg
  ; CHECK:   $r0, dead $noreg = tMOVi8 0, 5 /* CC::pl */, $cpsr
  ; CHECK:   tBX_RET 5 /* CC::pl */, killed $cpsr, implicit killed $r0
  ; CHECK: bb.1.land.rhs:
  ; CHECK:   liveins: $r1, $r2
  ; CHECK:   $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
  ; CHECK:   $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg
  ; CHECK:   tTAILJMPdND @branch_target, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit $r0, implicit $r1
  bb.0.entry:
    successors: %bb.1, %bb.2
    liveins: $r0, $r1, $r2

    renamable $r0 = tLDRBi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.command_set, align 4)
    dead renamable $r0, $cpsr = tLSLri killed renamable $r0, 24, 14 /* CC::al */, $noreg
    t2Bcc %bb.2, 4 /* CC::mi */, killed $cpsr

  bb.1.land.end:
    $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
    tBX_RET 14 /* CC::al */, $noreg, implicit $r0

  bb.2.land.rhs:
    liveins: $r1, $r2

    $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
    $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg
    tTAILJMPdND @branch_target, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit $r0, implicit $r1

...