# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s

---
name: load_global_s32_from_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX10: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:vgpr(p1) = COPY %0
    %2:vgpr(s32) = G_LOAD %1 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %2

...

# FIXME: This zext wouldn't select on its own.
---

name: load_global_s32_from_sgpr_zext_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1, $vgpr0

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_zext_vgpr
    ; GFX9: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_zext_vgpr
    ; GFX10: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(p1) = COPY %0
    %3:vgpr(s64) = G_ZEXT %1
    %4:vgpr(p1) = G_PTR_ADD %2, %3
    %5:vgpr(s32) = G_LOAD %4 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %5

...

# Test with zext lowered to G_MERGE_VALUES
---

name: load_global_s32_from_sgpr_merge_zext_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1, $vgpr0

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_merge_zext_vgpr
    ; GFX9: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_merge_zext_vgpr
    ; GFX10: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(p1) = COPY %0
    %zero:vgpr(s32) = G_CONSTANT i32 0
    %3:vgpr(s64) = G_MERGE_VALUES %1, %zero
    %4:vgpr(p1) = G_PTR_ADD %2, %3
    %5:vgpr(s32) = G_LOAD %4 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %5

...

---

name: load_global_s32_from_sgpr_merge_not_0_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1, $vgpr0

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_merge_not_0_vgpr
    ; GFX9: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
    ; GFX9: %notzero:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
    ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, %notzero, %subreg.sub1
    ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
    ; GFX9: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX9: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub1
    ; GFX9: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX9: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
    ; GFX9: %12:vgpr_32, dead %14:sreg_64_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GFX9: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %12, %subreg.sub1
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_merge_not_0_vgpr
    ; GFX10: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
    ; GFX10: %notzero:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, %notzero, %subreg.sub1
    ; GFX10: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
    ; GFX10: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub1
    ; GFX10: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
    ; GFX10: %12:vgpr_32, dead %14:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %12, %subreg.sub1
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(p1) = COPY %0
    %notzero:vgpr(s32) = G_CONSTANT i32 1
    %3:vgpr(s64) = G_MERGE_VALUES %1, %notzero
    %4:vgpr(p1) = G_PTR_ADD %2, %3
    %5:vgpr(s32) = G_LOAD %4 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %5

...

---

name: load_global_s32_from_sgpr_zext_vgpr_offset4095
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1, $vgpr0

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_zext_vgpr_offset4095
    ; GFX9: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[COPY1]], 4095, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_zext_vgpr_offset4095
    ; GFX10: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
    ; GFX10: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX10: %zext:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, %zero, %subreg.sub1
    ; GFX10: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
    ; GFX10: [[COPY4:%[0-9]+]]:vgpr_32 = COPY %zext.sub0
    ; GFX10: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub1
    ; GFX10: [[COPY6:%[0-9]+]]:vgpr_32 = COPY %zext.sub1
    ; GFX10: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
    ; GFX10: %24:vgpr_32, dead %26:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %24, %subreg.sub1
    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
    ; GFX10: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
    ; GFX10: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
    ; GFX10: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY7]], [[COPY8]], 0, implicit $exec
    ; GFX10: %14:vgpr_32, dead %16:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY9]], [[COPY10]], killed [[V_ADD_CO_U32_e64_3]], 0, implicit $exec
    ; GFX10: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_2]], %subreg.sub0, %14, %subreg.sub1
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[REG_SEQUENCE2]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(p1) = COPY %0
    %zero:vgpr(s32) = G_CONSTANT i32 0
    %zext:vgpr(s64) = G_MERGE_VALUES %1, %zero
    %4:vgpr(p1) = G_PTR_ADD %2, %zext
    %5:vgpr(s64) = G_CONSTANT i64 4095
    %6:vgpr(p1) = G_PTR_ADD %4, %5
    %7:vgpr(s32) = G_LOAD %6 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %7

...

---

name: load_global_s32_from_sgpr_zext_vgpr_offset_neg4096
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1, $vgpr0

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_zext_vgpr_offset_neg4096
    ; GFX9: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[COPY1]], -4096, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_zext_vgpr_offset_neg4096
    ; GFX10: liveins: $sgpr0_sgpr1, $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
    ; GFX10: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX10: %zext:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, %zero, %subreg.sub1
    ; GFX10: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
    ; GFX10: [[COPY4:%[0-9]+]]:vgpr_32 = COPY %zext.sub0
    ; GFX10: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub1
    ; GFX10: [[COPY6:%[0-9]+]]:vgpr_32 = COPY %zext.sub1
    ; GFX10: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY3]], [[COPY4]], 0, implicit $exec
    ; GFX10: %24:vgpr_32, dead %26:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY5]], [[COPY6]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %24, %subreg.sub1
    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963200, implicit $exec
    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
    ; GFX10: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
    ; GFX10: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
    ; GFX10: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY7]], [[COPY8]], 0, implicit $exec
    ; GFX10: %14:vgpr_32, dead %16:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY9]], [[COPY10]], killed [[V_ADD_CO_U32_e64_3]], 0, implicit $exec
    ; GFX10: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_2]], %subreg.sub0, %14, %subreg.sub1
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[REG_SEQUENCE2]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(p1) = COPY %0
    %zero:vgpr(s32) = G_CONSTANT i32 0
    %zext:vgpr(s64) = G_MERGE_VALUES %1, %zero
    %4:vgpr(p1) = G_PTR_ADD %2, %zext
    %5:vgpr(s64) = G_CONSTANT i64 -4096
    %6:vgpr(p1) = G_PTR_ADD %4, %5
    %7:vgpr(s32) = G_LOAD %6 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %7

...
---
name: load_global_s32_from_sgpr_base_offset_4096
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_4096
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_4096
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
    ; GFX10: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 4096
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...

---
name: load_global_s32_from_sgpr_base_offset_4097
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_4097
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 1, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_4097
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
    ; GFX10: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 1, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 4097
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...

---
name: load_global_s32_from_sgpr_base_offset_neg4097
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_neg4097
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294963199
    ; GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
    ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX9: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX9: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX9: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX9: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_neg4097
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294963199
    ; GFX10: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX10: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX10: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX10: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 -4097
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...

---
name: load_global_s32_from_sgpr_base_offset_2049
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_2049
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 2049, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_2049
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2048, implicit $exec
    ; GFX10: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 1, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 2049
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...

---
name: load_global_s32_from_sgpr_base_offset_neg2049
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_neg2049
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], -2049, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_neg2049
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294965247
    ; GFX10: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX10: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX10: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX10: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 -2049
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...
---
name: load_global_s32_from_sgpr_base_offset_4294967295
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_4294967295
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294963200, implicit $exec
    ; GFX9: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 4095, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_4294967295
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec
    ; GFX10: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[COPY]], [[V_MOV_B32_e32_]], 2047, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 4294967295
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...
---
name: load_global_s32_from_sgpr_base_offset_4294967296
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_4294967296
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX9: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX9: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX9: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX9: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_4294967296
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GFX10: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX10: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX10: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX10: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 4294967296
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...

---
name: load_global_s32_from_sgpr_base_offset_4294971390
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_4294971390
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4094
    ; GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX9: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX9: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX9: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX9: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_4294971390
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4094
    ; GFX10: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX10: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX10: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX10: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 4294971390
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...

---
name: load_global_s32_from_sgpr_base_offset_neg4294967295
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_neg4294967295
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
    ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX9: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX9: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX9: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX9: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_neg4294967295
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; GFX10: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX10: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX10: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX10: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 -4294967295
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...
---
name: load_global_s32_from_sgpr_base_offset_neg4294967296
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $sgpr0_sgpr1

    ; GFX9-LABEL: name: load_global_s32_from_sgpr_base_offset_neg4294967296
    ; GFX9: liveins: $sgpr0_sgpr1
    ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
    ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX9: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX9: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX9: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX9: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_sgpr_base_offset_neg4294967296
    ; GFX10: liveins: $sgpr0_sgpr1
    ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GFX10: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
    ; GFX10: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX10: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; GFX10: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
    ; GFX10: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def $scc, implicit $scc
    ; GFX10: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ; GFX10: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = G_CONSTANT i64 -4294967296
    %2:sgpr(p1) = G_PTR_ADD %0, %1
    %3:vgpr(p1) = COPY %2
    %4:vgpr(s32) = G_LOAD %3 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %4

...

---
name: load_global_s32_from_copy_undef_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    ; GFX9-LABEL: name: load_global_s32_from_copy_undef_sgpr
    ; GFX9: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY [[DEF]]
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_copy_undef_sgpr
    ; GFX10: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY [[DEF]]
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:sgpr(p1) = G_IMPLICIT_DEF
    %1:vgpr(p1) = COPY %0
    %2:vgpr(s32) = G_LOAD %1 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %2

...

---
name: load_global_s32_from_undef_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    ; GFX9-LABEL: name: load_global_s32_from_undef_vgpr
    ; GFX9: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
    ; GFX9: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX9: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    ; GFX10-LABEL: name: load_global_s32_from_undef_vgpr
    ; GFX10: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
    ; GFX10: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 0, 0, implicit $exec :: (load 4, addrspace 1)
    ; GFX10: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]]
    %0:vgpr(p1) = G_IMPLICIT_DEF
    %1:vgpr(s32) = G_LOAD %0 :: (load 4, align 4, addrspace 1)
    $vgpr0 = COPY %1

...