test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown- | FileCheck %s

define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_1_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #1
; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ult_2_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_2_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #2
; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_2_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #2
; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_3_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #3
; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_3_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #3
; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ugt <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_4_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #4
; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ult <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_4_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #4
; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ugt <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_5_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #5
; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ult <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_5_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #5
; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ugt <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_6_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #6
; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ult <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_6_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #6
; CHECK-NEXT:    cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ugt <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_7_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    movi v1.16b, #7
; CHECK-NEXT:    cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT:    ret
  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
  %3 = icmp ult <16 x i8> %2, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
  %4 = sext <16 x i1> %3 to <16 x i8>
  ret <16 x i8> %4
}

define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_1_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT:    add v1.8h, v0.8h, v1.8h
; CHECK-NEXT:    cmtst v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_2_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_2_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT:    add v1.8h, v0.8h, v1.8h
; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    cmeq v0.8h, v0.8h, #0
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_2_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #2
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_3_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #3
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_3_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #3
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_4_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #4
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_4_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #4
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_5_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #5
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_5_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #5
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_6_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #6
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_6_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #6
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_7_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #7
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_7_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #7
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_8_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #8
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_8_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #8
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_9_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #9
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_9_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #9
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_10_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #10
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_10_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #10
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_11_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #11
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_11_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #11
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_12_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #12
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_12_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #12
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_13_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #13
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_13_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #13
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_14_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #14
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ugt_14_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #14
; CHECK-NEXT:    cmhi v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ugt <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
; CHECK-LABEL: ult_15_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    movi v1.8h, #15
; CHECK-NEXT:    cmhi v0.8h, v1.8h, v0.8h
; CHECK-NEXT:    ret
  %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
  %3 = icmp ult <8 x i16> %2, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %4 = sext <8 x i1> %3 to <8 x i16>
  ret <8 x i16> %4
}

define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_1_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT:    add v1.4s, v0.4s, v1.4s
; CHECK-NEXT:    cmtst v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_2_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_2_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT:    add v1.4s, v0.4s, v1.4s
; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_2_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #2
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_3_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #3
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_3_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #3
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_4_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #4
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_4_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #4
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_5_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #5
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_5_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #5
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_6_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #6
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_6_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #6
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_7_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #7
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_7_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #7
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_8_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #8
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_8_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #8
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_9_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #9
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_9_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #9
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_10_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #10
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_10_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #10
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_11_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #11
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_11_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #11
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_12_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #12
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_12_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #12
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_13_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #13
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_13_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #13
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_14_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #14
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_14_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #14
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_15_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #15
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_15_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #15
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_16_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #16
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_16_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #16
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_17_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #17
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_17_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #17
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_18_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #18
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_18_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #18
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_19_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #19
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_19_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #19
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_20_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #20
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_20_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #20
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_21_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #21
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_21_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #21
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_22_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #22
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_22_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #22
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_23_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #23
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_23_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #23
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_24_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #24
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_24_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #24
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_25_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #25
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_25_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #25
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_26_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #26
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_26_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #26
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_27_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #27
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_27_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #27
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_28_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #28
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_28_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #28
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_29_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #29
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_29_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #29
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_30_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #30
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ugt_30_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #30
; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ugt <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
; CHECK-LABEL: ult_31_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    movi v1.4s, #31
; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
  %3 = icmp ult <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31>
  %4 = sext <4 x i1> %3 to <4 x i32>
  ret <4 x i32> %4
}

define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_1_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT:    add v1.2d, v0.2d, v1.2d
; CHECK-NEXT:    cmtst v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 1, i64 1>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_2_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT:    add v1.2d, v0.2d, v1.2d
; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    cmeq v0.2d, v0.2d, #0
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 2, i64 2>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_2_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #2
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 2, i64 2>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_3_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #3
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 3, i64 3>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_3_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #3
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 3, i64 3>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_4_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #4
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 4, i64 4>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_4_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #4
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 4, i64 4>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_5_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #5
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 5, i64 5>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_5_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #5
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 5, i64 5>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_6_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #6
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 6, i64 6>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_6_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #6
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 6, i64 6>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_7_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #7
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 7, i64 7>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_7_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #7
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 7, i64 7>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_8_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #8
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 8, i64 8>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_8_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #8
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 8, i64 8>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_9_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #9
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 9, i64 9>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_9_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #9
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 9, i64 9>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_10_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #10
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 10, i64 10>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_10_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #10
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 10, i64 10>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_11_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #11
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 11, i64 11>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_11_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #11
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 11, i64 11>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_12_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #12
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 12, i64 12>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_12_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #12
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 12, i64 12>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_13_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #13
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 13, i64 13>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_13_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #13
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 13, i64 13>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_14_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #14
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 14, i64 14>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_14_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #14
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 14, i64 14>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_15_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #15
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 15, i64 15>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_15_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #15
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 15, i64 15>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_16_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #16
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 16, i64 16>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_16_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #16
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 16, i64 16>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_17_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #17
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 17, i64 17>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_17_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #17
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 17, i64 17>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_18_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #18
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 18, i64 18>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_18_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #18
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 18, i64 18>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_19_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #19
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 19, i64 19>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_19_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #19
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 19, i64 19>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_20_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #20
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 20, i64 20>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_20_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #20
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 20, i64 20>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_21_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #21
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 21, i64 21>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_21_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #21
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 21, i64 21>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_22_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #22
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 22, i64 22>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_22_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #22
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 22, i64 22>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_23_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #23
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 23, i64 23>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_23_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #23
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 23, i64 23>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_24_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #24
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 24, i64 24>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_24_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #24
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 24, i64 24>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_25_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #25
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 25, i64 25>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_25_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #25
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 25, i64 25>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_26_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #26
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 26, i64 26>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_26_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #26
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 26, i64 26>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_27_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #27
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 27, i64 27>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_27_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #27
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 27, i64 27>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_28_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #28
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 28, i64 28>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_28_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #28
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 28, i64 28>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_29_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #29
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 29, i64 29>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_29_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #29
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 29, i64 29>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_30_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #30
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 30, i64 30>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_30_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #30
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 30, i64 30>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_31_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #31
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 31, i64 31>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_31_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #31
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 31, i64 31>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_32_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #32
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 32, i64 32>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_32_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #32
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 32, i64 32>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_33_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #33
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 33, i64 33>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_33_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #33
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 33, i64 33>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_34_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #34
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 34, i64 34>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_34_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #34
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 34, i64 34>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_35_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #35
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 35, i64 35>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_35_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #35
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 35, i64 35>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_36_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #36
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 36, i64 36>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_36_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #36
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 36, i64 36>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_37_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #37
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 37, i64 37>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_37_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #37
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 37, i64 37>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_38_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #38
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 38, i64 38>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_38_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #38
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 38, i64 38>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_39_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #39
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 39, i64 39>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_39_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #39
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 39, i64 39>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_40_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #40
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 40, i64 40>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_40_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #40
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 40, i64 40>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_41_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #41
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 41, i64 41>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_41_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #41
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 41, i64 41>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_42_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #42
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 42, i64 42>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_42_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #42
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 42, i64 42>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_43_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #43
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 43, i64 43>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_43_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #43
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 43, i64 43>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_44_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #44
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 44, i64 44>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_44_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #44
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 44, i64 44>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_45_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #45
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 45, i64 45>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_45_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #45
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 45, i64 45>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_46_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #46
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 46, i64 46>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_46_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #46
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 46, i64 46>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_47_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #47
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 47, i64 47>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_47_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #47
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 47, i64 47>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_48_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #48
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 48, i64 48>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_48_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #48
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 48, i64 48>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_49_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #49
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 49, i64 49>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_49_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #49
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 49, i64 49>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_50_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #50
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 50, i64 50>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_50_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #50
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 50, i64 50>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_51_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #51
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 51, i64 51>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_51_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #51
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 51, i64 51>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_52_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #52
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 52, i64 52>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_52_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #52
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 52, i64 52>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_53_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #53
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 53, i64 53>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_53_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #53
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 53, i64 53>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_54_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #54
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 54, i64 54>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_54_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #54
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 54, i64 54>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_55_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #55
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 55, i64 55>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_55_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #55
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 55, i64 55>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_56_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #56
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 56, i64 56>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_56_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #56
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 56, i64 56>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_57_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #57
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 57, i64 57>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_57_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #57
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 57, i64 57>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_58_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #58
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 58, i64 58>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_58_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #58
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 58, i64 58>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_59_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #59
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 59, i64 59>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_59_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #59
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 59, i64 59>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_60_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #60
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 60, i64 60>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_60_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #60
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 60, i64 60>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_61_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #61
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 61, i64 61>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_61_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #61
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 61, i64 61>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_62_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #62
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 62, i64 62>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_62_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #62
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ugt <2 x i64> %2, <i64 62, i64 62>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_63_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cnt v0.16b, v0.16b
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    mov w8, #63
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    ret
  %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
  %3 = icmp ult <2 x i64> %2, <i64 63, i64 63>
  %4 = sext <2 x i1> %3 to <2 x i64>
  ret <2 x i64> %4
}

declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)