test/CodeGen/AArch64/sve-split-trunc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s

define <vscale x 16 x i8> @trunc_i16toi8(<vscale x 16 x i16> %in) {
; CHECK-LABEL: trunc_i16toi8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 z0.b, z0.b, z1.b
; CHECK-NEXT:    ret
  %out = trunc <vscale x 16 x i16> %in to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %out
}

define <vscale x 16 x i8> @trunc_i32toi8(<vscale x 16 x i32> %in) {
; CHECK-LABEL: trunc_i32toi8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 z2.h, z2.h, z3.h
; CHECK-NEXT:    uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT:    uzp1 z0.b, z0.b, z2.b
; CHECK-NEXT:    ret
  %out = trunc <vscale x 16 x i32> %in to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %out
}

define <vscale x 8 x i16> @trunc_i32toi16(<vscale x 8 x i32> %in) {
; CHECK-LABEL: trunc_i32toi16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT:    ret
  %out = trunc <vscale x 8 x i32> %in to <vscale x 8 x i16>
  ret <vscale x 8 x i16> %out
}

define <vscale x 4 x i32> @trunc_i64toi32(<vscale x 4 x i64> %in) {
; CHECK-LABEL: trunc_i64toi32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT:    ret
  %out = trunc <vscale x 4 x i64> %in to <vscale x 4 x i32>
  ret <vscale x 4 x i32> %out
}

define <vscale x 8 x i16> @trunc_i64toi16(<vscale x 8 x i64> %in) {
; CHECK-LABEL: trunc_i64toi16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 z2.s, z2.s, z3.s
; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT:    ret
  %out = trunc <vscale x 8 x i64> %in to <vscale x 8 x i16>
  ret <vscale x 8 x i16> %out
}

define <vscale x 16 x i8> @trunc_i64toi8(<vscale x 16 x i64> %in) {
; CHECK-LABEL: trunc_i64toi8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 z6.s, z6.s, z7.s
; CHECK-NEXT:    uzp1 z4.s, z4.s, z5.s
; CHECK-NEXT:    uzp1 z2.s, z2.s, z3.s
; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT:    uzp1 z1.h, z4.h, z6.h
; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT:    uzp1 z0.b, z0.b, z1.b
; CHECK-NEXT:    ret
  %out = trunc <vscale x 16 x i64> %in to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %out
}