commit 4347f30e6bb4ea58810faf7ab5d560096800f04f
author Craig Topper <craig.topper@sifive.com> Thu Feb 18 23:00:18 2021 -0800
committer Copybara-Service <copybara-worker@google.com> Fri Feb 19 03:52:06 2021 -0800
tree eaad24181ff4834489d7562a4426a1d51cd47bb5
parent 73a13719e23e4abdf4139e403b4ef96b698da797

[RISCV] Prune unneeded indexed load/store pseudo instructions.

We were creating more combinations of value and index lmul than
we needed.

I've copied the loop structure used here from VPseudoAMOEI with
all data sew values instead of just 32/64.

Similar can be done for segment loads/store.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D97008

GitOrigin-RevId: cd4051ac802fdc5664a3432f57d99bbcb4c07a92

lib/Target/RISCV/RISCVInstrInfoVPseudos.td

diff --git a/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 33b7e78..afbab16 100644
--- a/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1286,15 +1286,22 @@
 
 multiclass VPseudoILoad {
   foreach eew = EEWList in {
-    foreach lmul = MxList.m in
-    foreach idx_lmul = MxSet<eew>.m in {
-      defvar LInfo = lmul.MX;
-      defvar Vreg = lmul.vrclass;
-      defvar IdxLInfo = idx_lmul.MX;
-      defvar IdxVreg = idx_lmul.vrclass;
-      let VLMul = lmul.value in {
-        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo : VPseudoILoadNoMask<Vreg, IdxVreg>;
-        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" : VPseudoILoadMask<Vreg, IdxVreg>;
+    foreach sew = EEWList in {
+      foreach lmul = MxSet<sew>.m in {
+        defvar octuple_lmul = octuple_from_str<lmul.MX>.ret;
+        // Calculate emul = eew * lmul / sew
+        defvar octuple_emul = !srl(!mul(eew, octuple_lmul), shift_amount<sew>.val);
+        if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+          defvar LInfo = lmul.MX;
+          defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+          defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
+          defvar Vreg = lmul.vrclass;
+          defvar IdxVreg = idx_lmul.vrclass;
+          let VLMul = lmul.value in {
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo : VPseudoILoadNoMask<Vreg, IdxVreg>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" : VPseudoILoadMask<Vreg, IdxVreg>;
+          }
+        }
       }
     }
   }
@@ -1336,17 +1343,24 @@
 
 multiclass VPseudoIStore {
   foreach eew = EEWList in {
-    foreach lmul = MxList.m in
-    foreach idx_lmul = MxSet<eew>.m in {
-      defvar LInfo = lmul.MX;
-      defvar Vreg = lmul.vrclass;
-      defvar IdxLInfo = idx_lmul.MX;
-      defvar IdxVreg = idx_lmul.vrclass;
-      let VLMul = lmul.value in {
-        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
-          VPseudoIStoreNoMask<Vreg, IdxVreg>;
-        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
-          VPseudoIStoreMask<Vreg, IdxVreg>;
+    foreach sew = EEWList in {
+      foreach lmul = MxSet<sew>.m in {
+        defvar octuple_lmul = octuple_from_str<lmul.MX>.ret;
+        // Calculate emul = eew * lmul / sew
+        defvar octuple_emul = !srl(!mul(eew, octuple_lmul), shift_amount<sew>.val);
+        if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+          defvar LInfo = lmul.MX;
+          defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
+          defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
+          defvar Vreg = lmul.vrclass;
+          defvar IdxVreg = idx_lmul.vrclass;
+          let VLMul = lmul.value in {
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
+              VPseudoIStoreNoMask<Vreg, IdxVreg>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
+              VPseudoIStoreMask<Vreg, IdxVreg>;
+          }
+        }
       }
     }
   }