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//===-- NVPTXISelLowering.cpp - NVPTX DAG Lowering Implementation ---------===//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// This file defines the interfaces that NVPTX uses to lower LLVM code into a
// selection DAG.
#include "NVPTXISelLowering.h"
#include "MCTargetDesc/NVPTXBaseInfo.h"
#include "NVPTX.h"
#include "NVPTXSubtarget.h"
#include "NVPTXTargetMachine.h"
#include "NVPTXTargetObjectFile.h"
#include "NVPTXUtilities.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/FPEnv.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsNVPTX.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cmath>
#include <cstdint>
#include <iterator>
#include <sstream>
#include <string>
#include <utility>
#include <vector>
#define DEBUG_TYPE "nvptx-lower"
using namespace llvm;
static std::atomic<unsigned> GlobalUniqueCallSite;
static cl::opt<bool> sched4reg(
cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
static cl::opt<unsigned> FMAContractLevelOpt(
"nvptx-fma-level", cl::Hidden,
cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
" 1: do it 2: do it aggressively"),
static cl::opt<int> UsePrecDivF32(
"nvptx-prec-divf32", cl::Hidden,
cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
" IEEE Compliant F32 div.rnd if available."),
static cl::opt<bool> UsePrecSqrtF32(
"nvptx-prec-sqrtf32", cl::Hidden,
cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
static cl::opt<bool> ForceMinByValParamAlign(
"nvptx-force-min-byval-param-align", cl::Hidden,
cl::desc("NVPTX Specific: force 4-byte minimal alignment for byval"
" params of device functions."),
int NVPTXTargetLowering::getDivF32Level() const {
if (UsePrecDivF32.getNumOccurrences() > 0) {
// If nvptx-prec-div32=N is used on the command-line, always honor it
return UsePrecDivF32;
} else {
// Otherwise, use div.approx if fast math is enabled
if (getTargetMachine().Options.UnsafeFPMath)
return 0;
return 2;
bool NVPTXTargetLowering::usePrecSqrtF32() const {
if (UsePrecSqrtF32.getNumOccurrences() > 0) {
// If nvptx-prec-sqrtf32 is used on the command-line, always honor it
return UsePrecSqrtF32;
} else {
// Otherwise, use sqrt.approx if fast math is enabled
return !getTargetMachine().Options.UnsafeFPMath;
bool NVPTXTargetLowering::useF32FTZ(const MachineFunction &MF) const {
return MF.getDenormalMode(APFloat::IEEEsingle()).Output ==
static bool IsPTXVectorType(MVT VT) {
switch (VT.SimpleTy) {
return false;
case MVT::v2i1:
case MVT::v4i1:
case MVT::v2i8:
case MVT::v4i8:
case MVT::v2i16:
case MVT::v4i16:
case MVT::v8i16: // <4 x i16x2>
case MVT::v2i32:
case MVT::v4i32:
case MVT::v2i64:
case MVT::v2f16:
case MVT::v4f16:
case MVT::v8f16: // <4 x f16x2>
case MVT::v2bf16:
case MVT::v4bf16:
case MVT::v8bf16: // <4 x bf16x2>
case MVT::v2f32:
case MVT::v4f32:
case MVT::v2f64:
return true;
static bool Is16bitsType(MVT VT) {
return (VT.SimpleTy == MVT::f16 || VT.SimpleTy == MVT::bf16 ||
VT.SimpleTy == MVT::i16);
/// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
/// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
/// into their primitive components.
/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
/// LowerCall, and LowerReturn.
static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
SmallVectorImpl<uint64_t> *Offsets = nullptr,
uint64_t StartingOffset = 0) {
SmallVector<EVT, 16> TempVTs;
SmallVector<uint64_t, 16> TempOffsets;
// Special case for i128 - decompose to (i64, i64)
if (Ty->isIntegerTy(128)) {
if (Offsets) {
Offsets->push_back(StartingOffset + 0);
Offsets->push_back(StartingOffset + 8);
// Given a struct type, recursively traverse the elements with custom ComputePTXValueVTs.
if (StructType *STy = dyn_cast<StructType>(Ty)) {
auto const *SL = DL.getStructLayout(STy);
auto ElementNum = 0;
for(auto *EI : STy->elements()) {
ComputePTXValueVTs(TLI, DL, EI, ValueVTs, Offsets,
StartingOffset + SL->getElementOffset(ElementNum));
ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
EVT VT = TempVTs[i];
uint64_t Off = TempOffsets[i];
// Split vectors into individual elements, except for v2f16, which
// we will pass as a single scalar.
if (VT.isVector()) {
unsigned NumElts = VT.getVectorNumElements();
EVT EltVT = VT.getVectorElementType();
// Vectors with an even number of f16 elements will be passed to
// us as an array of v2f16/v2bf16 elements. We must match this so we
// stay in sync with Ins/Outs.
if ((Is16bitsType(EltVT.getSimpleVT())) && NumElts % 2 == 0) {
switch (EltVT.getSimpleVT().SimpleTy) {
case MVT::f16:
EltVT = MVT::v2f16;
case MVT::bf16:
EltVT = MVT::v2bf16;
case MVT::i16:
EltVT = MVT::v2i16;
llvm_unreachable("Unexpected type");
NumElts /= 2;
for (unsigned j = 0; j != NumElts; ++j) {
if (Offsets)
Offsets->push_back(Off + j * EltVT.getStoreSize());
} else {
if (Offsets)
/// PromoteScalarIntegerPTX
/// Used to make sure the arguments/returns are suitable for passing
/// and promote them to a larger size if they're not.
/// The promoted type is placed in \p PromoteVT if the function returns true.
static bool PromoteScalarIntegerPTX(const EVT &VT, MVT *PromotedVT) {
if (VT.isScalarInteger()) {
switch (PowerOf2Ceil(VT.getFixedSizeInBits())) {
"Promotion is not suitable for scalars of size larger than 64-bits");
case 1:
*PromotedVT = MVT::i1;
case 2:
case 4:
case 8:
*PromotedVT = MVT::i8;
case 16:
*PromotedVT = MVT::i16;
case 32:
*PromotedVT = MVT::i32;
case 64:
*PromotedVT = MVT::i64;
return EVT(*PromotedVT) != VT;
return false;
// Check whether we can merge loads/stores of some of the pieces of a
// flattened function parameter or return value into a single vector
// load/store.
// The flattened parameter is represented as a list of EVTs and
// offsets, and the whole structure is aligned to ParamAlignment. This
// function determines whether we can load/store pieces of the
// parameter starting at index Idx using a single vectorized op of
// size AccessSize. If so, it returns the number of param pieces
// covered by the vector op. Otherwise, it returns 1.
static unsigned CanMergeParamLoadStoresStartingAt(
unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs,
const SmallVectorImpl<uint64_t> &Offsets, Align ParamAlignment) {
// Can't vectorize if param alignment is not sufficient.
if (ParamAlignment < AccessSize)
return 1;
// Can't vectorize if offset is not aligned.
if (Offsets[Idx] & (AccessSize - 1))
return 1;
EVT EltVT = ValueVTs[Idx];
unsigned EltSize = EltVT.getStoreSize();
// Element is too large to vectorize.
if (EltSize >= AccessSize)
return 1;
unsigned NumElts = AccessSize / EltSize;
// Can't vectorize if AccessBytes if not a multiple of EltSize.
if (AccessSize != EltSize * NumElts)
return 1;
// We don't have enough elements to vectorize.
if (Idx + NumElts > ValueVTs.size())
return 1;
// PTX ISA can only deal with 2- and 4-element vector ops.
if (NumElts != 4 && NumElts != 2)
return 1;
for (unsigned j = Idx + 1; j < Idx + NumElts; ++j) {
// Types do not match.
if (ValueVTs[j] != EltVT)
return 1;
// Elements are not contiguous.
if (Offsets[j] - Offsets[j - 1] != EltSize)
return 1;
// OK. We can vectorize ValueVTs[i..i+NumElts)
return NumElts;
// Flags for tracking per-element vectorization state of loads/stores
// of a flattened function parameter or return value.
enum ParamVectorizationFlags {
PVF_INNER = 0x0, // Middle elements of a vector.
PVF_FIRST = 0x1, // First element of the vector.
PVF_LAST = 0x2, // Last element of the vector.
// Scalar is effectively a 1-element vector.
// Computes whether and how we can vectorize the loads/stores of a
// flattened function parameter or return value.
// The flattened parameter is represented as the list of ValueVTs and
// Offsets, and is aligned to ParamAlignment bytes. We return a vector
// of the same size as ValueVTs indicating how each piece should be
// loaded/stored (i.e. as a scalar, or as part of a vector
// load/store).
static SmallVector<ParamVectorizationFlags, 16>
VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
const SmallVectorImpl<uint64_t> &Offsets,
Align ParamAlignment, bool IsVAArg = false) {
// Set vector size to match ValueVTs and mark all elements as
// scalars by default.
SmallVector<ParamVectorizationFlags, 16> VectorInfo;
VectorInfo.assign(ValueVTs.size(), PVF_SCALAR);
if (IsVAArg)
return VectorInfo;
// Check what we can vectorize using 128/64/32-bit accesses.
for (int I = 0, E = ValueVTs.size(); I != E; ++I) {
// Skip elements we've already processed.
assert(VectorInfo[I] == PVF_SCALAR && "Unexpected vector info state.");
for (unsigned AccessSize : {16, 8, 4, 2}) {
unsigned NumElts = CanMergeParamLoadStoresStartingAt(
I, AccessSize, ValueVTs, Offsets, ParamAlignment);
// Mark vectorized elements.
switch (NumElts) {
llvm_unreachable("Unexpected return value");
case 1:
// Can't vectorize using this size, try next smaller size.
case 2:
assert(I + 1 < E && "Not enough elements.");
VectorInfo[I] = PVF_FIRST;
VectorInfo[I + 1] = PVF_LAST;
I += 1;
case 4:
assert(I + 3 < E && "Not enough elements.");
VectorInfo[I] = PVF_FIRST;
VectorInfo[I + 1] = PVF_INNER;
VectorInfo[I + 2] = PVF_INNER;
VectorInfo[I + 3] = PVF_LAST;
I += 3;
// Break out of the inner loop because we've already succeeded
// using largest possible AccessSize.
return VectorInfo;
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
const NVPTXSubtarget &STI)
: TargetLowering(TM), nvTM(&TM), STI(STI) {
// always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather
// then generating calls to memset, mempcy or memmove.
MaxStoresPerMemset = MaxStoresPerMemsetOptSize = (unsigned)0xFFFFFFFF;
MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = (unsigned) 0xFFFFFFFF;
MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = (unsigned) 0xFFFFFFFF;
// Jump is Expensive. Don't create extra control flow for 'and', 'or'
// condition branches.
// Wide divides are _very_ slow. Try to reduce the width of the divide if
// possible.
addBypassSlowDiv(64, 32);
// By default, use the Source scheduling
if (sched4reg)
auto setFP16OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
LegalizeAction NoF16Action) {
setOperationAction(Op, VT, STI.allowFP16Math() ? Action : NoF16Action);
auto setBF16OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
LegalizeAction NoBF16Action) {
bool IsOpSupported = STI.hasBF16Math();
// Few instructions are available on sm_90 only
switch(Op) {
case ISD::FADD:
case ISD::FMUL:
case ISD::FSUB:
IsOpSupported = STI.getSmVersion() >= 90 && STI.getPTXVersion() >= 78;
Op, VT, IsOpSupported ? Action : NoBF16Action);
auto setI16x2OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
LegalizeAction NoI16x2Action) {
bool IsOpSupported = false;
// instructions are available on sm_90 only
switch (Op) {
case ISD::ADD:
case ISD::SMAX:
case ISD::SMIN:
case ISD::UMIN:
case ISD::UMAX:
case ISD::SUB:
IsOpSupported = STI.getSmVersion() >= 90 && STI.getPTXVersion() >= 80;
setOperationAction(Op, VT, IsOpSupported ? Action : NoI16x2Action);
addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
addRegisterClass(MVT::v2i16, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
addRegisterClass(MVT::f16, &NVPTX::Int16RegsRegClass);
addRegisterClass(MVT::v2f16, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::bf16, &NVPTX::Int16RegsRegClass);
addRegisterClass(MVT::v2bf16, &NVPTX::Int32RegsRegClass);
// Conversion to/from FP16/FP16x2 is always legal.
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand);
setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
// Conversion to/from BFP16/BFP16x2 is always legal.
setOperationAction(ISD::BUILD_VECTOR, MVT::v2bf16, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2bf16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2bf16, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2bf16, Expand);
setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote);
setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand);
// Conversion to/from i16/i16x2 is always legal.
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i16, Expand);
// Operations not directly supported by NVPTX.
for (MVT VT :
{MVT::bf16, MVT::f16, MVT::v2bf16, MVT::v2f16, MVT::f32, MVT::f64,
MVT::i1, MVT::i8, MVT::i16, MVT::v2i16, MVT::i32, MVT::i64}) {
setOperationAction(ISD::SELECT_CC, VT, Expand);
setOperationAction(ISD::BR_CC, VT, Expand);
// Some SIGN_EXTEND_INREG can be done using cvt instruction.
// For others we will expand to a SHL/SRA pair.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
// TODO: we may consider expanding ROTL/ROTR on older GPUs. Currently on GPUs
// that don't have h/w rotation we lower them to multi-instruction assembly.
// See ROT*_sw in
setOperationAction(ISD::ROTL, MVT::i64, Legal);
setOperationAction(ISD::ROTR, MVT::i64, Legal);
setOperationAction(ISD::ROTL, MVT::i32, Legal);
setOperationAction(ISD::ROTR, MVT::i32, Legal);
setOperationAction(ISD::ROTL, MVT::i16, Expand);
setOperationAction(ISD::ROTL, MVT::v2i16, Expand);
setOperationAction(ISD::ROTR, MVT::i16, Expand);
setOperationAction(ISD::ROTR, MVT::v2i16, Expand);
setOperationAction(ISD::ROTL, MVT::i8, Expand);
setOperationAction(ISD::ROTR, MVT::i8, Expand);
setOperationAction(ISD::BSWAP, MVT::i16, Expand);
setOperationAction(ISD::BSWAP, MVT::v2i16, Expand);
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
// Indirect branch is not supported.
// This also disables Jump Table creation.
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
// We want to legalize constant related memmove and memcopy
// intrinsics.
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
// Turn FP extload into load/fpextend
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::bf16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::bf16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2bf16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2bf16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4bf16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4bf16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
// Turn FP truncstore into trunc + store.
// FIXME: vector types should also be expanded
setTruncStoreAction(MVT::f32, MVT::f16, Expand);
setTruncStoreAction(MVT::f64, MVT::f16, Expand);
setTruncStoreAction(MVT::f32, MVT::bf16, Expand);
setTruncStoreAction(MVT::f64, MVT::bf16, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// PTX does not support load / store predicate registers
setOperationAction(ISD::LOAD, MVT::i1, Custom);
setOperationAction(ISD::STORE, MVT::i1, Custom);
for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
setTruncStoreAction(VT, MVT::i1, Expand);
// expand extload of vector of integers.
MVT::v2i8, Expand);
setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand);
// This is legal in NVPTX
setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
setOperationAction(ISD::ConstantFP, MVT::bf16, Legal);
// TRAP can be lowered to PTX trap
setOperationAction(ISD::TRAP, MVT::Other, Legal);
// Register custom handling for vector loads/stores
for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
if (IsPTXVectorType(VT)) {
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
// Support varargs.
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAARG, MVT::Other, Custom);
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
setOperationAction(ISD::VAEND, MVT::Other, Expand);
// Custom handling for i8 intrinsics
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
for (const auto& Ty : {MVT::i16, MVT::i32, MVT::i64}) {
setOperationAction(ISD::ABS, Ty, Legal);
setOperationAction(ISD::SMIN, Ty, Legal);
setOperationAction(ISD::SMAX, Ty, Legal);
setOperationAction(ISD::UMIN, Ty, Legal);
setOperationAction(ISD::UMAX, Ty, Legal);
setOperationAction(ISD::CTPOP, Ty, Legal);
setOperationAction(ISD::CTLZ, Ty, Legal);
setI16x2OperationAction(ISD::ABS, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::SMIN, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::SMAX, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::UMIN, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::UMAX, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::CTPOP, MVT::v2i16, Legal, Expand);
setI16x2OperationAction(ISD::CTLZ, MVT::v2i16, Legal, Expand);
setI16x2OperationAction(ISD::ADD, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::SUB, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::MUL, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::SHL, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::SREM, MVT::v2i16, Legal, Custom);
setI16x2OperationAction(ISD::UREM, MVT::v2i16, Legal, Custom);
// Other arithmetic and logic ops are unsupported.
setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SRA, ISD::SRL, ISD::MULHS,
MVT::v2i16, Expand);
setOperationAction(ISD::ADDC, MVT::i32, Legal);
setOperationAction(ISD::ADDE, MVT::i32, Legal);
setOperationAction(ISD::SUBC, MVT::i32, Legal);
setOperationAction(ISD::SUBE, MVT::i32, Legal);
if (STI.getPTXVersion() >= 43) {
setOperationAction(ISD::ADDC, MVT::i64, Legal);
setOperationAction(ISD::ADDE, MVT::i64, Legal);
setOperationAction(ISD::SUBC, MVT::i64, Legal);
setOperationAction(ISD::SUBE, MVT::i64, Legal);
setOperationAction(ISD::CTTZ, MVT::i16, Expand);
setOperationAction(ISD::CTTZ, MVT::v2i16, Expand);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i64, Expand);
// PTX does not directly support SELP of i1, so promote to i32 first
setOperationAction(ISD::SELECT, MVT::i1, Custom);
// PTX cannot multiply two i64s in a single instruction.
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
// We have some custom DAG combine patterns for these nodes
// setcc for f16x2 and bf16x2 needs special handling to prevent
// legalizer's attempt to scalarize it due to v2i1 not being legal.
if (STI.allowFP16Math() || STI.hasBF16Math())
// Promote fp16 arithmetic if fp16 hardware isn't available or the
// user passed --nvptx-no-fp16-math. The flag is useful because,
// although sm_53+ GPUs have some sort of FP16 support in
// hardware, only sm_53 and sm_60 have full implementation. Others
// only have token amount of hardware and are likely to run faster
// by using fp32 units instead.
for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
setFP16OperationAction(Op, MVT::f16, Legal, Promote);
setFP16OperationAction(Op, MVT::v2f16, Legal, Expand);
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
setBF16OperationAction(Op, MVT::v2bf16, Legal, Expand);
// bf16 must be promoted to f32.
if (getOperationAction(Op, MVT::bf16) == Promote)
AddPromotedToType(Op, MVT::bf16, MVT::f32);
// f16/f16x2 neg was introduced in PTX 60, SM_53.
const bool IsFP16FP16x2NegAvailable = STI.getSmVersion() >= 53 &&
STI.getPTXVersion() >= 60 &&
for (const auto &VT : {MVT::f16, MVT::v2f16})
setOperationAction(ISD::FNEG, VT,
IsFP16FP16x2NegAvailable ? Legal : Expand);
setBF16OperationAction(ISD::FNEG, MVT::bf16, Legal, Expand);
setBF16OperationAction(ISD::FNEG, MVT::v2bf16, Legal, Expand);
// (would be) Library functions.
// These map to conversion instructions for scalar FP types.
setOperationAction(Op, MVT::bf16, Legal);
setOperationAction(Op, MVT::f16, Legal);
setOperationAction(Op, MVT::f32, Legal);
setOperationAction(Op, MVT::f64, Legal);
setOperationAction(Op, MVT::v2f16, Expand);
setOperationAction(Op, MVT::v2bf16, Expand);
setOperationAction(ISD::FROUND, MVT::f16, Promote);
setOperationAction(ISD::FROUND, MVT::v2f16, Expand);
setOperationAction(ISD::FROUND, MVT::bf16, Promote);
setOperationAction(ISD::FROUND, MVT::v2bf16, Expand);
setOperationAction(ISD::FROUND, MVT::f32, Custom);
setOperationAction(ISD::FROUND, MVT::f64, Custom);
// 'Expand' implements FCOPYSIGN without calling an external library.
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::v2bf16, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
// These map to corresponding instructions for f32/f64. f16 must be
// promoted to f32. v2f16 is expanded to f16, which is then promoted
// to f32.
for (const auto &Op :
setOperationAction(Op, MVT::f16, Promote);
setOperationAction(Op, MVT::bf16, Promote);
setOperationAction(Op, MVT::f32, Legal);
setOperationAction(Op, MVT::f64, Legal);
setOperationAction(Op, MVT::v2f16, Expand);
setOperationAction(Op, MVT::v2bf16, Expand);
// max.f16, max.f16x2 and max.NaN are supported on sm_80+.
auto GetMinMaxAction = [&](LegalizeAction NotSm80Action) {
bool IsAtLeastSm80 = STI.getSmVersion() >= 80 && STI.getPTXVersion() >= 70;
return IsAtLeastSm80 ? Legal : NotSm80Action;
for (const auto &Op : {ISD::FMINNUM, ISD::FMAXNUM}) {
setFP16OperationAction(Op, MVT::f16, GetMinMaxAction(Promote), Promote);
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
setOperationAction(Op, MVT::f32, Legal);
setOperationAction(Op, MVT::f64, Legal);
setFP16OperationAction(Op, MVT::v2f16, GetMinMaxAction(Expand), Expand);
setBF16OperationAction(Op, MVT::v2bf16, Legal, Expand);
for (const auto &Op : {ISD::FMINIMUM, ISD::FMAXIMUM}) {
setFP16OperationAction(Op, MVT::f16, GetMinMaxAction(Expand), Expand);
setFP16OperationAction(Op, MVT::bf16, Legal, Expand);
setOperationAction(Op, MVT::f32, GetMinMaxAction(Expand));
setFP16OperationAction(Op, MVT::v2f16, GetMinMaxAction(Expand), Expand);
setBF16OperationAction(Op, MVT::v2bf16, Legal, Expand);
// No FEXP2, FLOG2. The PTX ex2 and log2 functions are always approximate.
// No FPOW or FREM in PTX.
// Now deduce the information based on the above mentioned
// actions
const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((NVPTXISD::NodeType)Opcode) {
return "NVPTXISD::CALL";
case NVPTXISD::Wrapper:
return "NVPTXISD::Wrapper";
case NVPTXISD::DeclareParam:
return "NVPTXISD::DeclareParam";
case NVPTXISD::DeclareScalarParam:
return "NVPTXISD::DeclareScalarParam";
case NVPTXISD::DeclareRet:
return "NVPTXISD::DeclareRet";
case NVPTXISD::DeclareScalarRet:
return "NVPTXISD::DeclareScalarRet";
case NVPTXISD::DeclareRetParam:
return "NVPTXISD::DeclareRetParam";
case NVPTXISD::PrintCall:
return "NVPTXISD::PrintCall";
case NVPTXISD::PrintConvergentCall:
return "NVPTXISD::PrintConvergentCall";
case NVPTXISD::PrintCallUni:
return "NVPTXISD::PrintCallUni";
case NVPTXISD::PrintConvergentCallUni:
return "NVPTXISD::PrintConvergentCallUni";
case NVPTXISD::LoadParam:
return "NVPTXISD::LoadParam";
case NVPTXISD::LoadParamV2:
return "NVPTXISD::LoadParamV2";
case NVPTXISD::LoadParamV4:
return "NVPTXISD::LoadParamV4";
case NVPTXISD::StoreParam:
return "NVPTXISD::StoreParam";
case NVPTXISD::StoreParamV2:
return "NVPTXISD::StoreParamV2";
case NVPTXISD::StoreParamV4:
return "NVPTXISD::StoreParamV4";
case NVPTXISD::StoreParamS32:
return "NVPTXISD::StoreParamS32";
case NVPTXISD::StoreParamU32:
return "NVPTXISD::StoreParamU32";
case NVPTXISD::CallArgBegin:
return "NVPTXISD::CallArgBegin";
case NVPTXISD::CallArg:
return "NVPTXISD::CallArg";
case NVPTXISD::LastCallArg:
return "NVPTXISD::LastCallArg";
case NVPTXISD::CallArgEnd:
return "NVPTXISD::CallArgEnd";
case NVPTXISD::CallVoid:
return "NVPTXISD::CallVoid";
case NVPTXISD::CallVal:
return "NVPTXISD::CallVal";
case NVPTXISD::CallSymbol:
return "NVPTXISD::CallSymbol";
case NVPTXISD::Prototype:
return "NVPTXISD::Prototype";
case NVPTXISD::MoveParam:
return "NVPTXISD::MoveParam";
case NVPTXISD::StoreRetval:
return "NVPTXISD::StoreRetval";
case NVPTXISD::StoreRetvalV2:
return "NVPTXISD::StoreRetvalV2";
case NVPTXISD::StoreRetvalV4:
return "NVPTXISD::StoreRetvalV4";
case NVPTXISD::PseudoUseParam:
return "NVPTXISD::PseudoUseParam";
case NVPTXISD::CallSeqBegin:
return "NVPTXISD::CallSeqBegin";
case NVPTXISD::CallSeqEnd:
return "NVPTXISD::CallSeqEnd";
case NVPTXISD::CallPrototype:
return "NVPTXISD::CallPrototype";
case NVPTXISD::ProxyReg:
return "NVPTXISD::ProxyReg";
case NVPTXISD::LoadV2:
return "NVPTXISD::LoadV2";
case NVPTXISD::LoadV4:
return "NVPTXISD::LoadV4";
return "NVPTXISD::LDGV2";
return "NVPTXISD::LDGV4";
return "NVPTXISD::LDUV2";
return "NVPTXISD::LDUV4";
case NVPTXISD::StoreV2:
return "NVPTXISD::StoreV2";
case NVPTXISD::StoreV4:
return "NVPTXISD::StoreV4";
return "NVPTXISD::IMAD";
return "NVPTXISD::SETP_F16X2";
case NVPTXISD::Dummy:
return "NVPTXISD::Dummy";
case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
case NVPTXISD::Tex1DFloatFloatLevel:
return "NVPTXISD::Tex1DFloatFloatLevel";
case NVPTXISD::Tex1DFloatFloatGrad:
return "NVPTXISD::Tex1DFloatFloatGrad";
case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
case NVPTXISD::Tex1DS32FloatLevel:
return "NVPTXISD::Tex1DS32FloatLevel";
case NVPTXISD::Tex1DS32FloatGrad:
return "NVPTXISD::Tex1DS32FloatGrad";
case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
case NVPTXISD::Tex1DU32FloatLevel:
return "NVPTXISD::Tex1DU32FloatLevel";
case NVPTXISD::Tex1DU32FloatGrad:
return "NVPTXISD::Tex1DU32FloatGrad";
case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
case NVPTXISD::Tex1DArrayFloatFloatLevel:
return "NVPTXISD::Tex1DArrayFloatFloatLevel";
case NVPTXISD::Tex1DArrayFloatFloatGrad:
return "NVPTXISD::Tex1DArrayFloatFloatGrad";
case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
case NVPTXISD::Tex1DArrayS32FloatLevel:
return "NVPTXISD::Tex1DArrayS32FloatLevel";
case NVPTXISD::Tex1DArrayS32FloatGrad:
return "NVPTXISD::Tex1DArrayS32FloatGrad";
case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
case NVPTXISD::Tex1DArrayU32FloatLevel:
return "NVPTXISD::Tex1DArrayU32FloatLevel";
case NVPTXISD::Tex1DArrayU32FloatGrad:
return "NVPTXISD::Tex1DArrayU32FloatGrad";
case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
case NVPTXISD::Tex2DFloatFloatLevel:
return "NVPTXISD::Tex2DFloatFloatLevel";
case NVPTXISD::Tex2DFloatFloatGrad:
return "NVPTXISD::Tex2DFloatFloatGrad";
case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
case NVPTXISD::Tex2DS32FloatLevel:
return "NVPTXISD::Tex2DS32FloatLevel";
case NVPTXISD::Tex2DS32FloatGrad:
return "NVPTXISD::Tex2DS32FloatGrad";
case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
case NVPTXISD::Tex2DU32FloatLevel:
return "NVPTXISD::Tex2DU32FloatLevel";
case NVPTXISD::Tex2DU32FloatGrad:
return "NVPTXISD::Tex2DU32FloatGrad";
case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
case NVPTXISD::Tex2DArrayFloatFloatLevel:
return "NVPTXISD::Tex2DArrayFloatFloatLevel";
case NVPTXISD::Tex2DArrayFloatFloatGrad:
return "NVPTXISD::Tex2DArrayFloatFloatGrad";
case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
case NVPTXISD::Tex2DArrayS32FloatLevel:
return "NVPTXISD::Tex2DArrayS32FloatLevel";
case NVPTXISD::Tex2DArrayS32FloatGrad:
return "NVPTXISD::Tex2DArrayS32FloatGrad";
case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
case NVPTXISD::Tex2DArrayU32FloatLevel:
return "NVPTXISD::Tex2DArrayU32FloatLevel";
case NVPTXISD::Tex2DArrayU32FloatGrad:
return "NVPTXISD::Tex2DArrayU32FloatGrad";
case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
case NVPTXISD::Tex3DFloatFloatLevel:
return "NVPTXISD::Tex3DFloatFloatLevel";
case NVPTXISD::Tex3DFloatFloatGrad:
return "NVPTXISD::Tex3DFloatFloatGrad";
case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
case NVPTXISD::Tex3DS32FloatLevel:
return "NVPTXISD::Tex3DS32FloatLevel";
case NVPTXISD::Tex3DS32FloatGrad:
return "NVPTXISD::Tex3DS32FloatGrad";
case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
case NVPTXISD::Tex3DU32FloatLevel:
return "NVPTXISD::Tex3DU32FloatLevel";
case NVPTXISD::Tex3DU32FloatGrad:
return "NVPTXISD::Tex3DU32FloatGrad";
case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
case NVPTXISD::TexCubeFloatFloatLevel:
return "NVPTXISD::TexCubeFloatFloatLevel";
case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
case NVPTXISD::TexCubeS32FloatLevel:
return "NVPTXISD::TexCubeS32FloatLevel";
case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
case NVPTXISD::TexCubeU32FloatLevel:
return "NVPTXISD::TexCubeU32FloatLevel";
case NVPTXISD::TexCubeArrayFloatFloat:
return "NVPTXISD::TexCubeArrayFloatFloat";
case NVPTXISD::TexCubeArrayFloatFloatLevel:
return "NVPTXISD::TexCubeArrayFloatFloatLevel";
case NVPTXISD::TexCubeArrayS32Float:
return "NVPTXISD::TexCubeArrayS32Float";
case NVPTXISD::TexCubeArrayS32FloatLevel:
return "NVPTXISD::TexCubeArrayS32FloatLevel";
case NVPTXISD::TexCubeArrayU32Float:
return "NVPTXISD::TexCubeArrayU32Float";
case NVPTXISD::TexCubeArrayU32FloatLevel:
return "NVPTXISD::TexCubeArrayU32FloatLevel";
case NVPTXISD::Tld4R2DFloatFloat:
return "NVPTXISD::Tld4R2DFloatFloat";
case NVPTXISD::Tld4G2DFloatFloat:
return "NVPTXISD::Tld4G2DFloatFloat";
case NVPTXISD::Tld4B2DFloatFloat:
return "NVPTXISD::Tld4B2DFloatFloat";
case NVPTXISD::Tld4A2DFloatFloat:
return "NVPTXISD::Tld4A2DFloatFloat";
case NVPTXISD::Tld4R2DS64Float:
return "NVPTXISD::Tld4R2DS64Float";
case NVPTXISD::Tld4G2DS64Float:
return "NVPTXISD::Tld4G2DS64Float";
case NVPTXISD::Tld4B2DS64Float:
return "NVPTXISD::Tld4B2DS64Float";
case NVPTXISD::Tld4A2DS64Float:
return "NVPTXISD::Tld4A2DS64Float";
case NVPTXISD::Tld4R2DU64Float:
return "NVPTXISD::Tld4R2DU64Float";
case NVPTXISD::Tld4G2DU64Float:
return "NVPTXISD::Tld4G2DU64Float";
case NVPTXISD::Tld4B2DU64Float:
return "NVPTXISD::Tld4B2DU64Float";
case NVPTXISD::Tld4A2DU64Float:
return "NVPTXISD::Tld4A2DU64Float";
case NVPTXISD::TexUnified1DFloatS32:
return "NVPTXISD::TexUnified1DFloatS32";
case NVPTXISD::TexUnified1DFloatFloat:
return "NVPTXISD::TexUnified1DFloatFloat";
case NVPTXISD::TexUnified1DFloatFloatLevel:
return "NVPTXISD::TexUnified1DFloatFloatLevel";
case NVPTXISD::TexUnified1DFloatFloatGrad:
return "NVPTXISD::TexUnified1DFloatFloatGrad";
case NVPTXISD::TexUnified1DS32S32:
return "NVPTXISD::TexUnified1DS32S32";
case NVPTXISD::TexUnified1DS32Float:
return "NVPTXISD::TexUnified1DS32Float";
case NVPTXISD::TexUnified1DS32FloatLevel:
return "NVPTXISD::TexUnified1DS32FloatLevel";
case NVPTXISD::TexUnified1DS32FloatGrad:
return "NVPTXISD::TexUnified1DS32FloatGrad";
case NVPTXISD::TexUnified1DU32S32:
return "NVPTXISD::TexUnified1DU32S32";
case NVPTXISD::TexUnified1DU32Float:
return "NVPTXISD::TexUnified1DU32Float";
case NVPTXISD::TexUnified1DU32FloatLevel:
return "NVPTXISD::TexUnified1DU32FloatLevel";
case NVPTXISD::TexUnified1DU32FloatGrad:
return "NVPTXISD::TexUnified1DU32FloatGrad";
case NVPTXISD::TexUnified1DArrayFloatS32:
return "NVPTXISD::TexUnified1DArrayFloatS32";
case NVPTXISD::TexUnified1DArrayFloatFloat:
return "NVPTXISD::TexUnified1DArrayFloatFloat";
case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
case NVPTXISD::TexUnified1DArrayS32S32:
return "NVPTXISD::TexUnified1DArrayS32S32";
case NVPTXISD::TexUnified1DArrayS32Float:
return "NVPTXISD::TexUnified1DArrayS32Float";
case NVPTXISD::TexUnified1DArrayS32FloatLevel:
return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
case NVPTXISD::TexUnified1DArrayS32FloatGrad:
return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
case NVPTXISD::TexUnified1DArrayU32S32:
return "NVPTXISD::TexUnified1DArrayU32S32";
case NVPTXISD::TexUnified1DArrayU32Float:
return "NVPTXISD::TexUnified1DArrayU32Float";
case NVPTXISD::TexUnified1DArrayU32FloatLevel:
return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
case NVPTXISD::TexUnified1DArrayU32FloatGrad:
return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
case NVPTXISD::TexUnified2DFloatS32:
return "NVPTXISD::TexUnified2DFloatS32";
case NVPTXISD::TexUnified2DFloatFloat:
return "NVPTXISD::TexUnified2DFloatFloat";
case NVPTXISD::TexUnified2DFloatFloatLevel:
return "NVPTXISD::TexUnified2DFloatFloatLevel";
case NVPTXISD::TexUnified2DFloatFloatGrad:
return "NVPTXISD::TexUnified2DFloatFloatGrad";
case NVPTXISD::TexUnified2DS32S32:
return "NVPTXISD::TexUnified2DS32S32";
case NVPTXISD::TexUnified2DS32Float:
return "NVPTXISD::TexUnified2DS32Float";
case NVPTXISD::TexUnified2DS32FloatLevel:
return "NVPTXISD::TexUnified2DS32FloatLevel";
case NVPTXISD::TexUnified2DS32FloatGrad:
return "NVPTXISD::TexUnified2DS32FloatGrad";
case NVPTXISD::TexUnified2DU32S32:
return "NVPTXISD::TexUnified2DU32S32";
case NVPTXISD::TexUnified2DU32Float:
return "NVPTXISD::TexUnified2DU32Float";
case NVPTXISD::TexUnified2DU32FloatLevel:
return "NVPTXISD::TexUnified2DU32FloatLevel";
case NVPTXISD::TexUnified2DU32FloatGrad:
return "NVPTXISD::TexUnified2DU32FloatGrad";
case NVPTXISD::TexUnified2DArrayFloatS32:
return "NVPTXISD::TexUnified2DArrayFloatS32";
case NVPTXISD::TexUnified2DArrayFloatFloat:
return "NVPTXISD::TexUnified2DArrayFloatFloat";
case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
case NVPTXISD::TexUnified2DArrayS32S32:
return "NVPTXISD::TexUnified2DArrayS32S32";
case NVPTXISD::TexUnified2DArrayS32Float:
return "NVPTXISD::TexUnified2DArrayS32Float";
case NVPTXISD::TexUnified2DArrayS32FloatLevel:
return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
case NVPTXISD::TexUnified2DArrayS32FloatGrad:
return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
case NVPTXISD::TexUnified2DArrayU32S32:
return "NVPTXISD::TexUnified2DArrayU32S32";
case NVPTXISD::TexUnified2DArrayU32Float:
return "NVPTXISD::TexUnified2DArrayU32Float";
case NVPTXISD::TexUnified2DArrayU32FloatLevel:
return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
case NVPTXISD::TexUnified2DArrayU32FloatGrad:
return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
case NVPTXISD::TexUnified3DFloatS32:
return "NVPTXISD::TexUnified3DFloatS32";
case NVPTXISD::TexUnified3DFloatFloat:
return "NVPTXISD::TexUnified3DFloatFloat";
case NVPTXISD::TexUnified3DFloatFloatLevel:
return "NVPTXISD::TexUnified3DFloatFloatLevel";
case NVPTXISD::TexUnified3DFloatFloatGrad:
return "NVPTXISD::TexUnified3DFloatFloatGrad";
case NVPTXISD::TexUnified3DS32S32:
return "NVPTXISD::TexUnified3DS32S32";
case NVPTXISD::TexUnified3DS32Float:
return "NVPTXISD::TexUnified3DS32Float";
case NVPTXISD::TexUnified3DS32FloatLevel:
return "NVPTXISD::TexUnified3DS32FloatLevel";
case NVPTXISD::TexUnified3DS32FloatGrad:
return "NVPTXISD::TexUnified3DS32FloatGrad";
case NVPTXISD::TexUnified3DU32S32:
return "NVPTXISD::TexUnified3DU32S32";
case NVPTXISD::TexUnified3DU32Float:
return "NVPTXISD::TexUnified3DU32Float";
case NVPTXISD::TexUnified3DU32FloatLevel:
return "NVPTXISD::TexUnified3DU32FloatLevel";
case NVPTXISD::TexUnified3DU32FloatGrad:
return "NVPTXISD::TexUnified3DU32FloatGrad";
case NVPTXISD::TexUnifiedCubeFloatFloat:
return "NVPTXISD::TexUnifiedCubeFloatFloat";
case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
case NVPTXISD::TexUnifiedCubeS32Float:
return "NVPTXISD::TexUnifiedCubeS32Float";
case NVPTXISD::TexUnifiedCubeS32FloatLevel:
return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
case NVPTXISD::TexUnifiedCubeU32Float:
return "NVPTXISD::TexUnifiedCubeU32Float";
case NVPTXISD::TexUnifiedCubeU32FloatLevel:
return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
case NVPTXISD::TexUnifiedCubeArrayS32Float:
return "NVPTXISD::TexUnifiedCubeArrayS32Float";
case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
case NVPTXISD::TexUnifiedCubeArrayU32Float:
return "NVPTXISD::TexUnifiedCubeArrayU32Float";
case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
case NVPTXISD::Tld4UnifiedR2DFloatFloat:
return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
case NVPTXISD::Tld4UnifiedG2DFloatFloat:
return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
case NVPTXISD::Tld4UnifiedB2DFloatFloat:
return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
case NVPTXISD::Tld4UnifiedA2DFloatFloat:
return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
case NVPTXISD::Tld4UnifiedR2DS64Float:
return "NVPTXISD::Tld4UnifiedR2DS64Float";
case NVPTXISD::Tld4UnifiedG2DS64Float:
return "NVPTXISD::Tld4UnifiedG2DS64Float";
case NVPTXISD::Tld4UnifiedB2DS64Float:
return "NVPTXISD::Tld4UnifiedB2DS64Float";
case NVPTXISD::Tld4UnifiedA2DS64Float:
return "NVPTXISD::Tld4UnifiedA2DS64Float";
case NVPTXISD::Tld4UnifiedR2DU64Float:
return "NVPTXISD::Tld4UnifiedR2DU64Float";
case NVPTXISD::Tld4UnifiedG2DU64Float:
return "NVPTXISD::Tld4UnifiedG2DU64Float";
case NVPTXISD::Tld4UnifiedB2DU64Float:
return "NVPTXISD::Tld4UnifiedB2DU64Float";
case NVPTXISD::Tld4UnifiedA2DU64Float:
return "NVPTXISD::Tld4UnifiedA2DU64Float";
case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
return nullptr;
NVPTXTargetLowering::getPreferredVectorAction(MVT VT) const {
if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
VT.getScalarType() == MVT::i1)
return TypeSplitVector;
if (Isv2x16VT(VT))
return TypeLegal;
return TargetLoweringBase::getPreferredVectorAction(VT);
SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled, int &ExtraSteps,
bool &UseOneConst,
bool Reciprocal) const {
if (!(Enabled == ReciprocalEstimate::Enabled ||
(Enabled == ReciprocalEstimate::Unspecified && !usePrecSqrtF32())))
return SDValue();
if (ExtraSteps == ReciprocalEstimate::Unspecified)
ExtraSteps = 0;
SDLoc DL(Operand);
EVT VT = Operand.getValueType();
bool Ftz = useF32FTZ(DAG.getMachineFunction());
auto MakeIntrinsicCall = [&](Intrinsic::ID IID) {
DAG.getConstant(IID, DL, MVT::i32), Operand);
// The sqrt and rsqrt refinement processes assume we always start out with an
// approximation of the rsqrt. Therefore, if we're going to do any refinement
// (i.e. ExtraSteps > 0), we must return an rsqrt. But if we're *not* doing
// any refinement, we must return a regular sqrt.
if (Reciprocal || ExtraSteps > 0) {
if (VT == MVT::f32)
return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_rsqrt_approx_ftz_f
: Intrinsic::nvvm_rsqrt_approx_f);
else if (VT == MVT::f64)
return MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d);
return SDValue();
} else {
if (VT == MVT::f32)
return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_sqrt_approx_ftz_f
: Intrinsic::nvvm_sqrt_approx_f);
else {
// There's no sqrt.approx.f64 instruction, so we emit
// reciprocal(rsqrt(x)). This is faster than
// select(x == 0, 0, x * rsqrt(x)). (In fact, it's faster than plain
// x * rsqrt(x).)
return DAG.getNode(
DAG.getConstant(Intrinsic::nvvm_rcp_approx_ftz_d, DL, MVT::i32),
NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
const GlobalAddressSDNode *GAN = cast<GlobalAddressSDNode>(Op);
auto PtrVT = getPointerTy(DAG.getDataLayout(), GAN->getAddressSpace());
Op = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, PtrVT);
return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
static bool IsTypePassedAsArray(const Type *Ty) {
return Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128) ||
Ty->isHalfTy() || Ty->isBFloatTy();
std::string NVPTXTargetLowering::getPrototype(
const DataLayout &DL, Type *retTy, const ArgListTy &Args,
const SmallVectorImpl<ISD::OutputArg> &Outs, MaybeAlign retAlignment,
std::optional<std::pair<unsigned, const APInt &>> VAInfo,
const CallBase &CB, unsigned UniqueCallSite) const {
auto PtrVT = getPointerTy(DL);
bool isABI = (STI.getSmVersion() >= 20);
assert(isABI && "Non-ABI compilation is not supported");
if (!isABI)
return "";
std::string Prototype;
raw_string_ostream O(Prototype);
O << "prototype_" << UniqueCallSite << " : .callprototype ";
if (retTy->getTypeID() == Type::VoidTyID) {
O << "()";
} else {
O << "(";
if ((retTy->isFloatingPointTy() || retTy->isIntegerTy()) &&
!IsTypePassedAsArray(retTy)) {
unsigned size = 0;
if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
size = ITy->getBitWidth();
} else {
assert(retTy->isFloatingPointTy() &&
"Floating point type expected here");
size = retTy->getPrimitiveSizeInBits();
// PTX ABI requires all scalar return values to be at least 32
// bits in size. fp16 normally uses .b16 as its storage type in
// PTX, so its size must be adjusted here, too.
size = promoteScalarArgumentSize(size);
O << ".param .b" << size << " _";
} else if (isa<PointerType>(retTy)) {
O << ".param .b" << PtrVT.getSizeInBits() << " _";
} else if (IsTypePassedAsArray(retTy)) {
O << ".param .align " << (retAlignment ? retAlignment->value() : 0)
<< " .b8 _[" << DL.getTypeAllocSize(retTy) << "]";
} else {
llvm_unreachable("Unknown return type");
O << ") ";
O << "_ (";
bool first = true;
const Function *F = CB.getFunction();
unsigned NumArgs = VAInfo ? VAInfo->first : Args.size();
for (unsigned i = 0, OIdx = 0; i != NumArgs; ++i, ++OIdx) {
Type *Ty = Args[i].Ty;
if (!first) {
O << ", ";
first = false;
if (!Outs[OIdx].Flags.isByVal()) {
if (IsTypePassedAsArray(Ty)) {
unsigned ParamAlign = 0;
const CallInst *CallI = cast<CallInst>(&CB);
// +1 because index 0 is reserved for return type alignment
if (!getAlign(*CallI, i + 1, ParamAlign))
ParamAlign = getFunctionParamOptimizedAlign(F, Ty, DL).value();
O << ".param .align " << ParamAlign << " .b8 ";
O << "_";
O << "[" << DL.getTypeAllocSize(Ty) << "]";
// update the index for Outs
SmallVector<EVT, 16> vtparts;
ComputeValueVTs(*this, DL, Ty, vtparts);
if (unsigned len = vtparts.size())
OIdx += len - 1;
// i8 types in IR will be i16 types in SDAG
assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
(getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
"type mismatch between callee prototype and arguments");
// scalar type
unsigned sz = 0;
if (isa<IntegerType>(Ty)) {
sz = cast<IntegerType>(Ty)->getBitWidth();
sz = promoteScalarArgumentSize(sz);
} else if (isa<PointerType>(Ty)) {
sz = PtrVT.getSizeInBits();
} else {
sz = Ty->getPrimitiveSizeInBits();
O << ".param .b" << sz << " ";
O << "_";
Type *ETy = Args[i].IndirectType;
Align InitialAlign = Outs[OIdx].Flags.getNonZeroByValAlign();
Align ParamByValAlign =
getFunctionByValParamAlign(F, ETy, InitialAlign, DL);
O << ".param .align " << ParamByValAlign.value() << " .b8 ";
O << "_";
O << "[" << Outs[OIdx].Flags.getByValSize() << "]";
if (VAInfo)
O << (first ? "" : ",") << " .param .align " << VAInfo->second
<< " .b8 _[]\n";
O << ")";
if (shouldEmitPTXNoReturn(&CB, *nvTM))
O << " .noreturn";
O << ";";
return Prototype;
Align NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
const CallBase *CB, Type *Ty,
unsigned Idx,
const DataLayout &DL) const {
if (!CB) {
// CallSite is zero, fallback to ABI type alignment
return DL.getABITypeAlign(Ty);
unsigned Alignment = 0;
const Function *DirectCallee = CB->getCalledFunction();
if (!DirectCallee) {
// We don't have a direct function symbol, but that may be because of
// constant cast instructions in the call.
// With bitcast'd call targets, the instruction will be the call
if (const auto *CI = dyn_cast<CallInst>(CB)) {
// Check if we have call alignment metadata
if (getAlign(*CI, Idx, Alignment))
return Align(Alignment);
DirectCallee = getMaybeBitcastedCallee(CB);
// Check for function alignment information if we found that the
// ultimate target is a Function
if (DirectCallee) {
if (getAlign(*DirectCallee, Idx, Alignment))
return Align(Alignment);
// If alignment information is not available, fall back to the
// default function param optimized type alignment
return getFunctionParamOptimizedAlign(DirectCallee, Ty, DL);
// Call is indirect, fall back to the ABI type alignment
return DL.getABITypeAlign(Ty);
SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const {
if (CLI.IsVarArg && (STI.getPTXVersion() < 60 || STI.getSmVersion() < 30))
"Support for variadic functions (unsized array parameter) introduced "
"in PTX ISA version 6.0 and requires target sm_30.");
SelectionDAG &DAG = CLI.DAG;
SDLoc dl = CLI.DL;
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
SDValue Chain = CLI.Chain;
SDValue Callee = CLI.Callee;
bool &isTailCall = CLI.IsTailCall;
ArgListTy &Args = CLI.getArgs();
Type *RetTy = CLI.RetTy;
const CallBase *CB = CLI.CB;
const DataLayout &DL = DAG.getDataLayout();
bool isABI = (STI.getSmVersion() >= 20);
assert(isABI && "Non-ABI compilation is not supported");
if (!isABI)
return Chain;
// Variadic arguments.
// Normally, for each argument, we declare a param scalar or a param
// byte array in the .param space, and store the argument value to that
// param scalar or array starting at offset 0.
// In the case of the first variadic argument, we declare a vararg byte array
// with size 0. The exact size of this array isn't known at this point, so
// it'll be patched later. All the variadic arguments will be stored to this
// array at a certain offset (which gets tracked by 'VAOffset'). The offset is
// initially set to 0, so it can be used for non-variadic arguments (which use
// 0 offset) to simplify the code.
// After all vararg is processed, 'VAOffset' holds the size of the
// vararg byte array.
SDValue VADeclareParam; // vararg byte array
unsigned FirstVAArg = CLI.NumFixedArgs; // position of the first variadic
unsigned VAOffset = 0; // current offset in the param array
unsigned UniqueCallSite = GlobalUniqueCallSite.fetch_add(1);
SDValue TempChain = Chain;
Chain = DAG.getCALLSEQ_START(Chain, UniqueCallSite, 0, dl);
SDValue InGlue = Chain.getValue(1);
unsigned ParamCount = 0;
// Args.size() and Outs.size() need not match.
// Outs.size() will be larger
// * if there is an aggregate argument with multiple fields (each field
// showing up separately in Outs)
// * if there is a vector argument with more than typical vector-length
// elements (generally if more than 4) where each vector element is
// individually present in Outs.
// So a different index should be used for indexing into Outs/OutVals.
// See similar issue in LowerFormalArguments.
unsigned OIdx = 0;
// Declare the .params or .reg need to pass values
// to the function
for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
EVT VT = Outs[OIdx].VT;
Type *Ty = Args[i].Ty;
bool IsVAArg = (i >= CLI.NumFixedArgs);
bool IsByVal = Outs[OIdx].Flags.isByVal();
SmallVector<EVT, 16> VTs;
SmallVector<uint64_t, 16> Offsets;
assert((!IsByVal || Args[i].IndirectType) &&
"byval arg must have indirect type");
Type *ETy = (IsByVal ? Args[i].IndirectType : Ty);
ComputePTXValueVTs(*this, DL, ETy, VTs, &Offsets, IsByVal ? 0 : VAOffset);
Align ArgAlign;
if (IsByVal) {
// The ByValAlign in the Outs[OIdx].Flags is always set at this point,
// so we don't need to worry whether it's naturally aligned or not.
// See TargetLowering::LowerCallTo().
Align InitialAlign = Outs[OIdx].Flags.getNonZeroByValAlign();
ArgAlign = getFunctionByValParamAlign(CB->getCalledFunction(), ETy,
InitialAlign, DL);
if (IsVAArg)
VAOffset = alignTo(VAOffset, ArgAlign);
} else {
ArgAlign = getArgumentAlignment(Callee, CB, Ty, ParamCount + 1, DL);
unsigned TypeSize =
(IsByVal ? Outs[OIdx].Flags.getByValSize() : DL.getTypeAllocSize(Ty));
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
bool NeedAlign; // Does argument declaration specify alignment?
bool PassAsArray = IsByVal || IsTypePassedAsArray(Ty);
if (IsVAArg) {
if (ParamCount == FirstVAArg) {
SDValue DeclareParamOps[] = {
Chain, DAG.getConstant(STI.getMaxRequiredAlignment(), dl, MVT::i32),
DAG.getConstant(ParamCount, dl, MVT::i32),
DAG.getConstant(1, dl, MVT::i32), InGlue};
VADeclareParam = Chain = DAG.getNode(NVPTXISD::DeclareParam, dl,
DeclareParamVTs, DeclareParamOps);
NeedAlign = PassAsArray;
} else if (PassAsArray) {
// declare .param .align <align> .b8 .param<n>[<size>];
SDValue DeclareParamOps[] = {
Chain, DAG.getConstant(ArgAlign.value(), dl, MVT::i32),
DAG.getConstant(ParamCount, dl, MVT::i32),
DAG.getConstant(TypeSize, dl, MVT::i32), InGlue};
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
NeedAlign = true;
} else {
// declare .param .b<size> .param<n>;
if (VT.isInteger() || VT.isFloatingPoint()) {
// PTX ABI requires integral types to be at least 32 bits in
// size. FP16 is loaded/stored using i16, so it's handled
// here as well.
TypeSize = promoteScalarArgumentSize(TypeSize * 8) / 8;
SDValue DeclareScalarParamOps[] = {
Chain, DAG.getConstant(ParamCount, dl, MVT::i32),
DAG.getConstant(TypeSize * 8, dl, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InGlue};
Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
NeedAlign = false;
InGlue = Chain.getValue(1);
// PTX Interoperability Guide 3.3(A): [Integer] Values shorter
// than 32-bits are sign extended or zero extended, depending on
// whether they are signed or unsigned types. This case applies
// only to scalar parameters and not to aggregate values.
bool ExtendIntegerParam =
Ty->isIntegerTy() && DL.getTypeAllocSizeInBits(Ty) < 32;
auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, ArgAlign, IsVAArg);
SmallVector<SDValue, 6> StoreOperands;
for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
EVT EltVT = VTs[j];
int CurOffset = Offsets[j];
MaybeAlign PartAlign;
if (NeedAlign)
PartAlign = commonAlignment(ArgAlign, CurOffset);
// New store.
if (VectorInfo[j] & PVF_FIRST) {
assert(StoreOperands.empty() && "Unfinished preceding store.");
DAG.getConstant(IsVAArg ? FirstVAArg : ParamCount, dl, MVT::i32));
IsByVal ? CurOffset + VAOffset : (IsVAArg ? VAOffset : CurOffset),
dl, MVT::i32));
SDValue StVal = OutVals[OIdx];
MVT PromotedVT;
if (PromoteScalarIntegerPTX(EltVT, &PromotedVT)) {
EltVT = EVT(PromotedVT);
if (PromoteScalarIntegerPTX(StVal.getValueType(), &PromotedVT)) {
llvm::ISD::NodeType Ext =
Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
StVal = DAG.getNode(Ext, dl, PromotedVT, StVal);
if (IsByVal) {
auto PtrVT = getPointerTy(DL);
SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StVal,
DAG.getConstant(CurOffset, dl, PtrVT));
StVal = DAG.getLoad(EltVT, dl, TempChain, srcAddr, MachinePointerInfo(),
} else if (ExtendIntegerParam) {
assert(VTs.size() == 1 && "Scalar can't have multiple parts.");
// zext/sext to i32
StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
dl, MVT::i32, StVal);
if (!ExtendIntegerParam && EltVT.getSizeInBits() < 16) {
// Use 16-bit registers for small stores as it's the
// smallest general purpose register size supported by NVPTX.
StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
// Record the value to store.
if (VectorInfo[j] & PVF_LAST) {
unsigned NumElts = StoreOperands.size() - 3;
NVPTXISD::NodeType Op;
switch (NumElts) {
case 1:
Op = NVPTXISD::StoreParam;
case 2:
Op = NVPTXISD::StoreParamV2;
case 4:
Op = NVPTXISD::StoreParamV4;
llvm_unreachable("Invalid vector info.");
// Adjust type of the store op if we've extended the scalar
// return value.
EVT TheStoreType = ExtendIntegerParam ? MVT::i32 : EltVT;
Chain = DAG.getMemIntrinsicNode(
Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
TheStoreType, MachinePointerInfo(), PartAlign,
InGlue = Chain.getValue(1);
// Cleanup.
// TODO: We may need to support vector types that can be passed
// as scalars in variadic arguments.
if (!IsByVal && IsVAArg) {
assert(NumElts == 1 &&
"Vectorization is expected to be disabled for variadics.");
VAOffset += DL.getTypeAllocSize(
if (!IsByVal)
assert(StoreOperands.empty() && "Unfinished parameter store.");
if (!IsByVal && VTs.size() > 0)
if (IsByVal && IsVAArg)
VAOffset += TypeSize;
GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
MaybeAlign retAlignment = std::nullopt;
// Handle Result
if (Ins.size() > 0) {
SmallVector<EVT, 16> resvtparts;
ComputeValueVTs(*this, DL, RetTy, resvtparts);
// Declare
// .param .align N .b8 retval0[<size-in-bytes>], or
// .param .b<size-in-bits> retval0
unsigned resultsz = DL.getTypeAllocSizeInBits(RetTy);
if (!IsTypePassedAsArray(RetTy)) {
resultsz = promoteScalarArgumentSize(resultsz);
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
DAG.getConstant(resultsz, dl, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InGlue };
Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
InGlue = Chain.getValue(1);
} else {
retAlignment = getArgumentAlignment(Callee, CB, RetTy, 0, DL);
assert(retAlignment && "retAlignment is guaranteed to be set");
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue DeclareRetOps[] = {
Chain, DAG.getConstant(retAlignment->value(), dl, MVT::i32),
DAG.getConstant(resultsz / 8, dl, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InGlue};
Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
InGlue = Chain.getValue(1);
bool HasVAArgs = CLI.IsVarArg && (CLI.Args.size() > CLI.NumFixedArgs);
// Set the size of the vararg param byte array if the callee is a variadic
// function and the variadic part is not empty.
if (HasVAArgs) {
SDValue DeclareParamOps[] = {
VADeclareParam.getOperand(0), VADeclareParam.getOperand(1),
VADeclareParam.getOperand(2), DAG.getConstant(VAOffset, dl, MVT::i32),
DAG.MorphNodeTo(VADeclareParam.getNode(), VADeclareParam.getOpcode(),
VADeclareParam->getVTList(), DeclareParamOps);
// Both indirect calls and libcalls have nullptr Func. In order to distinguish
// between them we must rely on the call site value which is valid for
// indirect calls but is always null for libcalls.
bool isIndirectCall = !Func && CB;
if (isa<ExternalSymbolSDNode>(Callee)) {
Function* CalleeFunc = nullptr;
// Try to find the callee in the current module.
Callee = DAG.getSymbolFunctionGlobalAddress(Callee, &CalleeFunc);
assert(CalleeFunc != nullptr && "Libcall callee must be set.");
// Set the "libcall callee" attribute to indicate that the function
// must always have a declaration.
CalleeFunc->addFnAttr("nvptx-libcall-callee", "true");
if (isIndirectCall) {
// This is indirect function call case : PTX requires a prototype of the
// form
// proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
// to be emitted, and the label has to used as the last arg of call
// instruction.
// The prototype is embedded in a string and put as the operand for a
// CallPrototype SDNode which will print out to the value of the string.
SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
std::string Proto = getPrototype(
DL, RetTy, Args, Outs, retAlignment,
? std::optional<std::pair<unsigned, const APInt &>>(std::make_pair(
: std::nullopt,
*CB, UniqueCallSite);
const char *ProtoStr = nvTM->getStrPool().save(Proto).data();
SDValue ProtoOps[] = {
DAG.getTargetExternalSymbol(ProtoStr, MVT::i32),
Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
InGlue = Chain.getValue(1);
// Op to just print "call"
SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue PrintCallOps[] = {
Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InGlue
// We model convergent calls as separate opcodes.
unsigned Opcode = isIndirectCall ? NVPTXISD::PrintCall : NVPTXISD::PrintCallUni;
if (CLI.IsConvergent)
Opcode = Opcode == NVPTXISD::PrintCallUni ? NVPTXISD::PrintConvergentCallUni
: NVPTXISD::PrintConvergentCall;
Chain = DAG.getNode(Opcode, dl, PrintCallVTs, PrintCallOps);
InGlue = Chain.getValue(1);
// Ops to print out the function name
SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CallVoidOps[] = { Chain, Callee, InGlue };
Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
InGlue = Chain.getValue(1);
// Ops to print out the param list
SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CallArgBeginOps[] = { Chain, InGlue };
Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
InGlue = Chain.getValue(1);
for (unsigned i = 0, e = std::min(CLI.NumFixedArgs + 1, ParamCount); i != e;
++i) {
unsigned opcode;
if (i == (e - 1))
opcode = NVPTXISD::LastCallArg;
opcode = NVPTXISD::CallArg;
SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
DAG.getConstant(i, dl, MVT::i32), InGlue };
Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
InGlue = Chain.getValue(1);
SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CallArgEndOps[] = { Chain,
DAG.getConstant(isIndirectCall ? 0 : 1, dl, MVT::i32),
InGlue };
Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
InGlue = Chain.getValue(1);
if (isIndirectCall) {
SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue PrototypeOps[] = {
Chain, DAG.getConstant(UniqueCallSite, dl, MVT::i32), InGlue};
Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
InGlue = Chain.getValue(1);
SmallVector<SDValue, 16> ProxyRegOps;
SmallVector<std::optional<MVT>, 16> ProxyRegTruncates;
// Generate loads from param memory/moves from registers for result
if (Ins.size() > 0) {
SmallVector<EVT, 16> VTs;
SmallVector<uint64_t, 16> Offsets;
ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0);
assert(VTs.size() == Ins.size() && "Bad value decomposition");
Align RetAlign = getArgumentAlignment(Callee, CB, RetTy, 0, DL);
auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, RetAlign);
SmallVector<EVT, 6> LoadVTs;
int VecIdx = -1; // Index of the first element of the vector.
// PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
// 32-bits are sign extended or zero extended, depending on whether
// they are signed or unsigned types.
bool ExtendIntegerRetVal =
RetTy->isIntegerTy() && DL.getTypeAllocSizeInBits(RetTy) < 32;
for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
bool needTruncate = false;
EVT TheLoadType = VTs[i];
EVT EltType = Ins[i].VT;
Align EltAlign = commonAlignment(RetAlign, Offsets[i]);
MVT PromotedVT;
if (PromoteScalarIntegerPTX(TheLoadType, &PromotedVT)) {
TheLoadType = EVT(PromotedVT);
EltType = EVT(PromotedVT);
needTruncate = true;
if (ExtendIntegerRetVal) {
TheLoadType = MVT::i32;
EltType = MVT::i32;
needTruncate = true;
} else if (TheLoadType.getSizeInBits() < 16) {
if (VTs[i].isInteger())
needTruncate = true;
EltType = MVT::i16;
// Record index of the very first element of the vector.
if (VectorInfo[i] & PVF_FIRST) {
assert(VecIdx == -1 && LoadVTs.empty() && "Orphaned operand list.");
VecIdx = i;
if (VectorInfo[i] & PVF_LAST) {
unsigned NumElts = LoadVTs.size();
NVPTXISD::NodeType Op;
switch (NumElts) {
case 1:
Op = NVPTXISD::LoadParam;
case 2:
Op = NVPTXISD::LoadParamV2;
case 4:
Op = NVPTXISD::LoadParamV4;
llvm_unreachable("Invalid vector info.");
SDValue LoadOperands[] = {
Chain, DAG.getConstant(1, dl, MVT::i32),
DAG.getConstant(Offsets[VecIdx], dl, MVT::i32), InGlue};
SDValue RetVal = DAG.getMemIntrinsicNode(
Op, dl, DAG.getVTList(LoadVTs), LoadOperands, TheLoadType,
MachinePointerInfo(), EltAlign,
for (unsigned j = 0; j < NumElts; ++j) {
if (needTruncate)
ProxyRegTruncates.push_back(std::optional<MVT>(Ins[VecIdx + j].VT));
Chain = RetVal.getValue(NumElts);
InGlue = RetVal.getValue(NumElts + 1);
// Cleanup
VecIdx = -1;
Chain =
DAG.getCALLSEQ_END(Chain, UniqueCallSite, UniqueCallSite + 1, InGlue, dl);
InGlue = Chain.getValue(1);
// Append ProxyReg instructions to the chain to make sure that `callseq_end`
// will not get lost. Otherwise, during libcalls expansion, the nodes can become
// dangling.
for (unsigned i = 0; i < ProxyRegOps.size(); ++i) {
SDValue Ret = DAG.getNode(
NVPTXISD::ProxyReg, dl,
DAG.getVTList(ProxyRegOps[i].getSimpleValueType(), MVT::Other, MVT::Glue),
{ Chain, ProxyRegOps[i], InGlue }
Chain = Ret.getValue(1);
InGlue = Ret.getValue(2);
if (ProxyRegTruncates[i]) {
Ret = DAG.getNode(ISD::TRUNCATE, dl, *ProxyRegTruncates[i], Ret);
// set isTailCall to false for now, until we figure out how to express
// tail call optimization in PTX
isTailCall = false;
return Chain;
// By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
// (see LegalizeDAG.cpp). This is slow and uses local memory.
// We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
SDNode *Node = Op.getNode();
SDLoc dl(Node);
SmallVector<SDValue, 8> Ops;
unsigned NumOperands = Node->getNumOperands();
for (unsigned i = 0; i < NumOperands; ++i) {
SDValue SubOp = Node->getOperand(i);
EVT VVT = SubOp.getNode()->getValueType(0);
EVT EltVT = VVT.getVectorElementType();
unsigned NumSubElem = VVT.getVectorNumElements();
for (unsigned j = 0; j < NumSubElem; ++j) {
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
DAG.getIntPtrConstant(j, dl)));
return DAG.getBuildVector(Node->getValueType(0), dl, Ops);
// We can init constant f16x2 with a single .b32 move. Normally it
// would get lowered as two constant loads and vector-packing move.
// mov.b16 %h1, 0x4000;
// mov.b16 %h2, 0x3C00;
// mov.b32 %hh2, {%h2, %h1};
// Instead we want just a constant move:
// mov.b32 %hh2, 0x40003C00
// This results in better SASS code with CUDA 7.x. Ptxas in CUDA 8.0
// generates good SASS in both cases.
SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
EVT VT = Op->getValueType(0);
if (!(Isv2x16VT(VT)))
return Op;
APInt E0;
APInt E1;
if (VT == MVT::v2f16 || VT == MVT::v2bf16) {
if (!(isa<ConstantFPSDNode>(Op->getOperand(0)) &&
return Op;
E0 = cast<ConstantFPSDNode>(Op->getOperand(0))
E1 = cast<ConstantFPSDNode>(Op->getOperand(1))
} else {
assert(VT == MVT::v2i16);
if (!(isa<ConstantSDNode>(Op->getOperand(0)) &&
return Op;
E0 = cast<ConstantSDNode>(Op->getOperand(0))->getAPIntValue();
E1 = cast<ConstantSDNode>(Op->getOperand(1))->getAPIntValue();
SDValue Const =
DAG.getConstant(E1.zext(32).shl(16) | E0.zext(32), SDLoc(Op), MVT::i32);
return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op->getValueType(0), Const);
SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const {
SDValue Index = Op->getOperand(1);
// Constant index will be matched by tablegen.
if (isa<ConstantSDNode>(Index.getNode()))
return Op;
// Extract individual elements and select one of them.
SDValue Vector = Op->getOperand(0);
EVT VectorVT = Vector.getValueType();
assert(Isv2x16VT(VectorVT) && "Unexpected vector type.");
EVT EltVT = VectorVT.getVectorElementType();
SDLoc dl(Op.getNode());
SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
DAG.getIntPtrConstant(0, dl));
SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
DAG.getIntPtrConstant(1, dl));
return DAG.getSelectCC(dl, Index, DAG.getIntPtrConstant(0, dl), E0, E1,
/// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
/// amount, or
/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
/// amount.
SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
SelectionDAG &DAG) const {
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
EVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits();
SDLoc dl(Op);
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
if (VTBits == 32 && STI.getSmVersion() >= 35) {
// For 32bit and sm35, we can use the funnel shift 'shf' instruction.
// {dHi, dLo} = {aHi, aLo} >> Amt
// dHi = aHi >> Amt
// dLo = shf.r.clamp aLo, aHi, Amt
SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, dl);
else {
// {dHi, dLo} = {aHi, aLo} >> Amt
// - if (Amt>=size) then
// dLo = aHi >> (Amt-size)
// dHi = aHi >> Amt (this is either all 0 or all 1)
// else
// dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
// dHi = aHi >> Amt
SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
DAG.getConstant(VTBits, dl, MVT::i32),
SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32));
SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32),
SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, dl);
/// LowerShiftLeftParts - Lower SHL_PARTS, which
/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
/// amount, or
/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
/// amount.
SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
SelectionDAG &DAG) const {
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
assert(Op.getOpcode() == ISD::SHL_PARTS);
EVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits();
SDLoc dl(Op);
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
if (VTBits == 32 && STI.getSmVersion() >= 35) {
// For 32bit and sm35, we can use the funnel shift 'shf' instruction.
// {dHi, dLo} = {aHi, aLo} << Amt
// dHi = shf.l.clamp aLo, aHi, Amt
// dLo = aLo << Amt
SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, dl);
else {
// {dHi, dLo} = {aHi, aLo} << Amt
// - if (Amt>=size) then
// dLo = aLo << Amt (all 0)
// dLo = aLo << (Amt-size)
// else
// dLo = aLo << Amt
// dHi = (aHi << Amt) | (aLo >> (size-Amt))
SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
DAG.getConstant(VTBits, dl, MVT::i32),
SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32));
SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32),
SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, dl);
SDValue NVPTXTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
if (VT == MVT::f32)
return LowerFROUND32(Op, DAG);
if (VT == MVT::f64)
return LowerFROUND64(Op, DAG);
llvm_unreachable("unhandled type");
// This is the the rounding method used in CUDA libdevice in C like code:
// float roundf(float A)
// {
// float RoundedA = (float) (int) ( A > 0 ? (A + 0.5f) : (A - 0.5f));
// RoundedA = abs(A) > 0x1.0p23 ? A : RoundedA;
// return abs(A) < 0.5 ? (float)(int)A : RoundedA;
// }
SDValue NVPTXTargetLowering::LowerFROUND32(SDValue Op,
SelectionDAG &DAG) const {
SDLoc SL(Op);
SDValue A = Op.getOperand(0);
EVT VT = Op.getValueType();
SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A);
// RoundedA = (float) (int) ( A > 0 ? (A + 0.5f) : (A - 0.5f))
SDValue Bitcast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, A);
const int SignBitMask = 0x80000000;
SDValue Sign = DAG.getNode(ISD::AND, SL, MVT::i32, Bitcast,
DAG.getConstant(SignBitMask, SL, MVT::i32));
const int PointFiveInBits = 0x3F000000;
SDValue PointFiveWithSignRaw =
DAG.getNode(ISD::OR, SL, MVT::i32, Sign,
DAG.getConstant(PointFiveInBits, SL, MVT::i32));
SDValue PointFiveWithSign =
DAG.getNode(ISD::BITCAST, SL, VT, PointFiveWithSignRaw);
SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign);
SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA);
// RoundedA = abs(A) > 0x1.0p23 ? A : RoundedA;
EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
SDValue IsLarge =
DAG.getSetCC(SL, SetCCVT, AbsA, DAG.getConstantFP(pow(2.0, 23.0), SL, VT),
RoundedA = DAG.getNode(ISD::SELECT, SL, VT, IsLarge, A, RoundedA);
// return abs(A) < 0.5 ? (float)(int)A : RoundedA;
SDValue IsSmall =DAG.getSetCC(SL, SetCCVT, AbsA,
DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT);
SDValue RoundedAForSmallA = DAG.getNode(ISD::FTRUNC, SL, VT, A);
return DAG.getNode(ISD::SELECT, SL, VT, IsSmall, RoundedAForSmallA, RoundedA);
// The implementation of round(double) is similar to that of round(float) in
// that they both separate the value range into three regions and use a method
// specific to the region to round the values. However, round(double) first
// calculates the round of the absolute value and then adds the sign back while
// round(float) directly rounds the value with sign.
SDValue NVPTXTargetLowering::LowerFROUND64(SDValue Op,
SelectionDAG &DAG) const {
SDLoc SL(Op);
SDValue A = Op.getOperand(0);
EVT VT = Op.getValueType();
SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A);
// double RoundedA = (double) (int) (abs(A) + 0.5f);
SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA,
DAG.getConstantFP(0.5, SL, VT));
SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA);
// RoundedA = abs(A) < 0.5 ? (double)0 : RoundedA;
EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
SDValue IsSmall =DAG.getSetCC(SL, SetCCVT, AbsA,
DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT);
RoundedA = DAG.getNode(ISD::SELECT, SL, VT, IsSmall,
DAG.getConstantFP(0, SL, VT),
// Add sign to rounded_A
RoundedA = DAG.getNode(ISD::FCOPYSIGN, SL, VT, RoundedA, A);
DAG.getNode(ISD::FTRUNC, SL, VT, A);
// RoundedA = abs(A) > 0x1.0p52 ? A : RoundedA;
SDValue IsLarge =
DAG.getSetCC(SL, SetCCVT, AbsA, DAG.getConstantFP(pow(2.0, 52.0), SL, VT),
return DAG.getNode(ISD::SELECT, SL, VT, IsLarge, A, RoundedA);
static SDValue LowerVectorArith(SDValue Op, SelectionDAG &DAG) {
SDLoc DL(Op);
if (Op.getValueType() != MVT::v2i16)
return Op;
EVT EltVT = Op.getValueType().getVectorElementType();
SmallVector<SDValue> VecElements;
for (int I = 0, E = Op.getValueType().getVectorNumElements(); I < E; I++) {
SmallVector<SDValue> ScalarArgs;
llvm::transform(Op->ops(), std::back_inserter(ScalarArgs),
[&](const SDUse &O) {
O.get(), DAG.getIntPtrConstant(I, DL));
VecElements.push_back(DAG.getNode(Op.getOpcode(), DL, EltVT, ScalarArgs));
SDValue V =
DAG.getNode(ISD::BUILD_VECTOR, DL, Op.getValueType(), VecElements);
return V;
NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
return SDValue();
return SDValue();
case ISD::GlobalAddress:
return LowerGlobalAddress(Op, DAG);
return Op;
return LowerBUILD_VECTOR(Op, DAG);
return Op;
return LowerCONCAT_VECTORS(Op, DAG);
case ISD::STORE:
return LowerSTORE(Op, DAG);
case ISD::LOAD:
return LowerLOAD(Op, DAG);
return LowerShiftLeftParts(Op, DAG);
return LowerShiftRightParts(Op, DAG);
return LowerSelect(Op, DAG);
return LowerFROUND(Op, DAG);
case ISD::VAARG:
return LowerVAARG(Op, DAG);
return LowerVASTART(Op, DAG);
case ISD::ABS:
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:<