test/CodeGen/Thumb2/peephole-addsub.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
--- |
  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv7-none-eabi"

  define i32 @test(i32 %a, i32 %b) {
    unreachable
  }

...
---
name:            test
tracksRegLiveness: true
liveins:
  - { reg: '$r0', virtual-reg: '%0' }
  - { reg: '$r1', virtual-reg: '%1' }
body:             |
  bb.0 (%ir-block.0):
    liveins: $r0, $r1

    ; CHECK-LABEL: name: test
    ; CHECK: liveins: $r0, $r1
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, $noreg
    ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2ADDrr]], 0, 14 /* CC::al */, $noreg, def $cpsr
    ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 0, 7 /* CC::vc */, $cpsr
    ; CHECK: $r0 = COPY [[t2MOVCCi]]
    ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
    %1:rgpr = COPY $r1
    %0:rgpr = COPY $r0
    %2:rgpr = t2MOVi 1, 14, $noreg, $noreg
    %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
    %4:rgpr = t2SUBri %3, 0, 14, $noreg, def dead $cpsr
    t2CMPri killed %3, 0, 14, $noreg, implicit-def $cpsr
    %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
    $r0 = COPY %5
    tBX_RET 14, $noreg, implicit $r0

...