# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s
# ARM load store optimizer was dealing with a sequence like:
#     s1 = VLDRS [r0, 1], implicit-def Q0
#     s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0
#     s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0
#     s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0
#
# It decided to combine the {s0, s1} loads into a single instruction in the
# third position. However, this leaves the instruction defining s3 with a stray
# imp-use of Q0, which is undefined.
#
# The verifier catches this, so this test just makes sure that appropriate
# liveness flags are added.
--- |
  target triple = "thumbv7-apple-ios"
  define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) {
    ret <4 x float> undef
  }
...
---
name:            foo
alignment:       2
liveins:
  - { reg: '$r0' }
body:             |
  bb.0 (%ir-block.0):
    liveins: $r0

    ; CHECK-LABEL: name: foo
    ; CHECK: $s3 = VLDRS $r0, 2, 14 /* CC::al */, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4)
    ; CHECK: VLDMSIA $r0, 14 /* CC::al */, $noreg, def $s0, def $s1, implicit-def $noreg :: (load 4)
    ; CHECK: $s2 = VLDRS killed $r0, 4, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
    ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
    $s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load 4)
    $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)

    $s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)

    $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)

    tBX_RET 14, $noreg, implicit $q0
...