test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s  | FileCheck %s
#
# Check for liveness errors when spilling partially defined super registers.

---
name:  sgpr_spill_s64_undef_high32
tracksRegLiveness: true
machineFunctionInfo:
  isEntryFunction: true
  hasSpilledSGPRs:     true
  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
  stackPtrOffsetReg: '$sgpr32'

stack:
  - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }

body:             |
  bb.0:
    liveins: $sgpr4

    ; CHECK-LABEL: name: sgpr_spill_s64_undef_high32
    ; CHECK: liveins: $sgpr4, $vgpr0
    ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
    ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5
    SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)

...

---
name:  sgpr_spill_s64_undef_low32
tracksRegLiveness: true
machineFunctionInfo:
  isEntryFunction: true
  hasSpilledSGPRs:     true
  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
  stackPtrOffsetReg: '$sgpr32'

stack:
  - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }

body:             |
  bb.0:
    liveins: $sgpr5

    ; CHECK-LABEL: name: sgpr_spill_s64_undef_low32
    ; CHECK: liveins: $sgpr5, $vgpr0
    ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
    ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5
    SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)

...