test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir

# RUN: llc -march=amdgcn -mcpu=gfx900 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

# Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.

# GCN-LABEL: {{^}}lo_to_lo_sgpr_to_vgpr:
# GCN: v_mov_b32_sdwa v1, s0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
name: lo_to_lo_sgpr_to_vgpr
tracksRegLiveness: true
body:             |
  bb.0:
    $sgpr0 = IMPLICIT_DEF
    $vgpr1_lo16 = COPY $sgpr0_lo16
    S_ENDPGM 0
...

# GCN-LABEL: {{^}}lo_to_hi_sgpr_to_vgpr:
# GCN: v_mov_b32_sdwa v1, s0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
name: lo_to_hi_sgpr_to_vgpr
tracksRegLiveness: true
body:             |
  bb.0:
    $sgpr0 = IMPLICIT_DEF
    $vgpr1_hi16 = COPY killed $sgpr0_lo16
    S_ENDPGM 0
...