| commit | 7d85ea51a35c1c5e86dfa7ddf849d4a5eac92431 | [log] [tgz] |
|---|---|---|
| author | Emmmer <yjhdandan@163.com> | Thu Jul 28 15:38:33 2022 +0800 |
| committer | Copybara-Service <copybara-worker@google.com> | Fri Jul 29 21:11:39 2022 -0700 |
| tree | 6b55112a6ae87d64d93f2d29337184db0814176c | |
| parent | 43a79b3a018dc04935dc0c75bdc0ca9776cfd19e [diff] |
[LLDB][RISCV] Add DWARF Registers According to [RISC-V DWARF Specification](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc) add RISCV DWARF Registers. Don't worry about the difference between riscv32 and riscv64, they just have different bytes of registers. Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D130686 GitOrigin-RevId: f473558647705a042de9d5ec96c23a21f2005bb1